參數(shù)資料
型號(hào): HYB39S128400CT-75
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128-MBit Synchronous DRAM
中文描述: 128兆位同步DRAM
文件頁(yè)數(shù): 19/51頁(yè)
文件大?。?/td> 470K
代理商: HYB39S128400CT-75
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies
19
9.01
3. If clock rising time is longer than 1 ns, a time (
t
/2
0.5) ns has to be added to this parameter.
4. If
t
is longer than 1 ns, a time (
t
1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycles and depend on the operating frequency
of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in fractions as a whole
number)
6. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.
7. The write recovery time twr = 2 CLK cycles is a digital interlock on this device. Special devices
with twr = 1 CLK for operations at less or equal 83 MHz will be available.
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
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