參數(shù)資料
型號: HYB39S128400CT-75
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128-MBit Synchronous DRAM
中文描述: 128兆位同步DRAM
文件頁數(shù): 9/51頁
文件大?。?/td> 470K
代理商: HYB39S128400CT-75
HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies
9
9.01
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Device
State
CKE
n-1
CKE
n
DQM
BA0
BA1
AP=
A10
Addr
A11,
A9-0
CS
RAS
CAS
WE
Bank Active
Idle
3
H
X
X
V
V
V
L
L
H
H
Bank Precharge
Any
H
X
X
V
L
X
L
L
H
L
Precharge All
Any
H
X
X
X
H
X
L
L
H
L
Write
Active
3
H
X
X
V
L
V
L
H
L
L
Write with Autoprecharge
Active
3
H
X
X
V
H
V
L
H
L
L
Read
Active
3
H
X
X
V
L
V
L
H
L
H
Read with Autoprecharge
Active
3
H
X
X
V
H
V
L
H
L
H
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
No Operation
Any
H
X
X
X
X
X
L
H
H
H
Burst Stop
Active
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
Auto Refresh
Idle
H
H
X
X
X
X
L
L
L
H
Self Refresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Self Refresh Exit
Idle
(Self
Refr.)
L
H
X
X
X
X
H
X
X
X
L
H
H
X
Power Down Entry
(Precharge or active
standby)
Idle
Active
4
H
L
X
X
X
X
H
X
X
X
L
H
H
X
Power Down Exit
Any
(Power
Down)
L
H
X
X
X
X
H
X
X
X
L
H
H
L
Data Write/Output Enable
Active
H
X
L
X
X
X
X
X
X
X
Data Write/Output Disable
Active
H
X
H
X
X
X
X
X
X
X
Notes:
1. V = Valid, x = Don
t Care, L = Low Level, H = High Level.
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock
before the commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Power Down Mode can not entry in the burst cycle. When this command is asserted in the burst
mode cycle the device is in clock suspend mode.
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