參數(shù)資料
型號(hào): HYB39S16400CT-10
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 16 MBit Synchronous DRAM
中文描述: 4M X 4 SYNCHRONOUS DRAM, 7 ns, PDSO50
封裝: 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP-50
文件頁(yè)數(shù): 5/19頁(yè)
文件大小: 101K
代理商: HYB39S16400CT-10
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
5
1998-10-01
Block Diagram for HYB 39S16400CT (2 banks
×
2 M
×
4 SDRAM)
V
DD
V
SS
V
DDQ
V
SSQ
Supply –
Power and ground for the input buffers and the core logic.
Supply –
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
Signal Pin Description
(cont’d)
Pin
Type
Signal Polarity Function
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
A
CLK Buffer
CLK
Row
Address
Counter
CS Buffer
RAS Buffer
CAS Buffer
WE Buffer
DQM Buffer
CS
RAS
CAS
WE
DQM
C
Self
Refresh Clock
CKE Buffer
CKE
2048 x 1024
Memory Bank A
and DQ Gate
Sense Amplifiers
Row/Column
Select
Bank A
Predecode A
Sequential
Control
Bank A
Mode Register
Control
Bank B
Predecode B
Sequential
Row/Column
Select
Bank B
Row Decoder
Data Latches
Data Latches
and DQ Gate
Row Decoder
Memory Bank B
2048 x 1024
Sense Amplifiers
D
2048
8
4
12
8
8
12
11
11
11
3
3
8
2048
DQ0
DQ1
DQ2
DQ3
Column Decoder
Column Decoder
SPB02835
1024
1024
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