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| 型號： | HYE18P32160AC-125 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | M39012 MIL RF CONNECTOR |
| 中文描述： | 32M的同步突發(fā)的CellularRAM |
| 文件頁數(shù)： | 16/53頁 |
| 文件大?。?/td> | 1426K |
| 代理商： | HYE18P32160AC-125 |
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HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Overview
Data Sheet
16
V2.0, 2003-12-16
1.6.3
In bi-directional synchronous mode read and write operations are performed on a complete synchronous base. To
put the device in full synchronous mode the Bus Configuration Register must be programmed first accordingly.
Table 8
shows the truth table for the supported synchronous read/write commands.
Commands Supported in Synchronous Mode
Note:‘L’ represents a low voltage level, ‘H’ a high voltage level, ‘X’ represents “Don’t Care”, ‘V’ represents “Valid”.
Table 8
Synchronous Command Table (Full Synchronous Mode)
Operation Mode
Power Mode
CLK
CS
ADV WE
UB/
LB
1)
X
1) OE does the same function to all DQ pins with UB and LB during read operation.
2)
Table 8
reflects the behaviour if UB and LB are asserted to low. If only either of the signals, UB or LB, is asserted to low
only the corresponding data byte will be output or written (UB enables DQ15 - DQ8, LB enables DQ7 - DQ0). If both signals
are disabled the device is put in deselect mode.
3) Output driver controlled by the asynchronous OE control signal
4) Stand-by power mode applies only to the case when CS goes low from DESELECT while no address change occurs. NO
OPERATION from any active power mode by keeping CS low consumes the power higher than stand-by mode.
5) The asynchronous OE control signal has to be asserted to ‘H’.
6) Deep power down is maintained until control register is re-programmed to disable the bit for deep power down (RCR Bit 4).
CRE A19
A20 - A0
DQ15:0
BURST INIT
READ
BURST READ
BURST INIT
WRITE
BURST WRITE
SET CONTROL
REGISTER
NO OPERATION
DESELECT
DPD
6)
Active
L->H
L
L
H
L
V
ADR
X
Active
Active
L->H
L->H
L
L
H
L
X
L
L
2)
X
X
L
X
V
X
ADR
DOUT
3)
X
Active
Active
L->H
L->H
L
L
H
L
X
L
L
2)
X
X
H
X
L
H
X
X
X
X
RCR DIN
BCR DIN
X
X
X
DIN
X
Standby~Active
4)
Standby
Deep Power Down L
L->H
L->H
L
H
H
H
X
X
H
X
X
X
X
X
L
X
X
High-Z
5)
High-Z
High-Z
Table 9
Mode
BURST INIT
Description of Commands in Synchronous Mode
Description
The BURST INIT command is used to initiate a synchronous burst access and to
latch the burst start address. The burst length is determined by the setting in the
Bus Configuration Register.
BURST READ
The BURST READ command is used to perform a synchronous burst read
access. The first data is output after the number of clock cycles as defined by the
programmed latency mode.
BURST WRITE
The BURST WRITE command is used to perform a synchronous burst write
access. The point of time when the first data is written is indicated by the WAIT
signal. It varies with the selected clock frequency and the occurrence of a refresh
cycle.
SET CONTROL REGISTER
The control registers are loaded via the address inputs A19, A15 - A0 performing
a single word burst. Please refer to the control register description for details. The
SCR command can only be issued when the CellularRAM is in idle state and no
bursts are in progress.
NO OPERATION
The NOP command is used to perform a no operation to the CellularRAM, which
is selected (CS = 0). Operations already in progress are not affected.
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