參數(shù)資料
型號(hào)： HYE18P32160AC-125
廠商： INFINEON TECHNOLOGIES AG
英文描述： M39012 MIL RF CONNECTOR
中文描述： 32M的同步突發(fā)的CellularRAM
文件頁(yè)數(shù)： 43/53頁(yè)
文件大?。?/td> 1426K
代理商： HYE18P32160AC-125
Data Sheet
43
V2.0, 2003-12-16
HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.8
Synchronous Mode
[Disclaimer]
WAIT signal of all synchronous timings below is shown in the case of WC=0 (at delay) and WP=0 (active low) though it is not
default state.
In synchronous mode, read and write operations are synchronized to the clock. Refresh cycles or page boundary
crossings are indicated to the host system by asserting the WAIT signal which in turn stalls the processor. WAIT
polarity, WAIT timing, synchronicity to the falling/rising clock edge, the burst length and further options are user
configurable and can be programmed via the bus configuration register (BCR).
2.8.1
Refer to
Section 2.7.1
and
Section 2.7.2
. All the timing and parameters are same as described in read operation
for NOR-Flash-Type mode.
Synchronous Read Mode Including Burst Suspend
2.8.2
In synchronous write mode, UB and LB are used as byte control of data input mask. At the rising edge of CLK,
their state is sampled and determined whether the coupled byte (DQ15-8 for UB and DQ7-0 for LB) is updated by
input data. Proper set-up time and hold time to CLK should be met. As discussed in
Section 2.4
, synchronous
burst write is always configured as continuous and no wrap, so that it has to be terminated by CS high state after
the burst fulfills required length of cycles.
Synchronous Write Mode
Figure 25
Synchronous Write Burst
Hi-z
Don't Care
CS
OE
UB, LB
WE
DQ15-DQ0
t
HD
A20-A0
ADR
CLK
WAIT
ADV
t
SP
t
CSS
t
CLK
t
CKH
t
CKL
t
HD
t
HD
in case the burst write access collides
with an ongoing refresh cycle additional
WAIT cycles might be inserted
D0
D1
D2
D3
D4
t
WZ
t
CBPH
t
WK
t
CWT
Latency Code2
t
SP
t
HD
(mask)
t
VP
t
VPH
t
HD
t
SP
t
SP
t
SP
相關(guān)PDF資料
PDF描述
HYE18P32160AC-15 M39012 MIL RF CONNECTOR
HYE18P32161AC-85 32M Asynchronous/Page CellularRAM
HYE18P32161AC 32M Asynchronous/Page CellularRAM
HYE18P32161ACL70 JT 23C 21#20 2#16 SKT PLUG
HYE18P32161ACL85 Circular Connector; MIL SPEC:MIL-DTL-38999 Series II; Body Material:Metal; Series:JT; No. of Contacts:11; Connector Shell Size:18; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYE18P32160AC-15 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Synchronous Burst CellularRAM
HYE18P32160AC-96 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Synchronous Burst CellularRAM
HYE18P32160ACL125 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Synchronous Burst CellularRAM
HYE18P32160ACL15 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Synchronous Burst CellularRAM
HYE18P32160ACL96 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Synchronous Burst CellularRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*