參數(shù)資料
型號: HYE18P32160AC-125
廠商: INFINEON TECHNOLOGIES AG
英文描述: M39012 MIL RF CONNECTOR
中文描述: 32M的同步突發(fā)的CellularRAM
文件頁數(shù): 52/53頁
文件大小: 1426K
代理商: HYE18P32160AC-125
D7
HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Appendix B: S/W Register Entry Mode (“4-cycle method”)
Data Sheet
52
V2.0, 2003-12-16
Figure 33
RCR Mapping in S/W Register Entry
Figure 34
BCR Mapping in S/W Register Entry
PASR
refreshed memory area
D2
D1
D0
Partial Array Self Refresh
0
0
1
0
1
0
D0
entire memory array (def.)
0
0
0
D1
D2
D3
D4
D5
D6
D7
D8
D15
TCSR
PM
0
0
max. case temp.
D5
Temperature-Compensated
Self-Refresh
1
+85°C (def.)
+70°C
+45°C
+15°C
0
1
0
D6
1
0
0
1
DQ<15:0>
Control Register
power down
Deep Power Down Mode
disabled (def.)
X
D4
0
1
1
lower 1/2 of memory array
lower 1/4 of memory array
lower 1/8 of memory array
1
0
1
1
1
0
1
1
1
upper 1/2 of memory array
upper 1/4 of memory array
upper 1/8 of memory array
DPD*
0
zero
1
0
0
page mode
Page Mode Bit
disabled (def.)
enabled
0
1
D7
D15....D8, D3:
reserved, must be set to '0'.
Burst Length
length
D2
D1
D0
all others reserved
continuous (def)
1
1
1
Burst Length
8
0
1
0
D0
4
0
0
1
D1
D2
D3
D4
D5
D6
D8
D9
D10
D11
D12
D13
D14
D15
BW
0
0
WP
WC
IMP
1
0
OM
wrap mode
Output Impedance
D5
full drive (def)
1/4 drive
0
1
Latency Mode
latency
all others reserved
Latency Mode
0
0
1
reserved
0
0
0
reserved
code3 (def)
0
1
1
polarity
WAIT# Polarity
D10
active low
active high (def)
0
1
opmode
Operation Mode
sync mode
0
1
D15
DQ <15:0>
Control Register
16
0
1
1
0
timing
WAIT# Configuration
D8
at delay
one data cycle in
advance (def)
0
1
async./ page mode (def)
wrap mode
Burst Wrap
D3
wrap
no wrap (def)
0
1
D11
D12
D13
code2
0
1
0
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