參數(shù)資料
型號: HYE18P32160ACL96
廠商: INFINEON TECHNOLOGIES AG
元件分類: 圓形連接器
英文描述: Circular Connector; MIL SPEC:MIL-DTL-38999 Series II; Body Material:Metal; Series:JT; No. of Contacts:11; Connector Shell Size:18; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No
中文描述: 32M的同步突發(fā)的CellularRAM
文件頁數(shù): 27/53頁
文件大?。?/td> 1426K
代理商: HYE18P32160ACL96
Data Sheet
27
V2.0, 2003-12-16
HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.4.1
The latency mode defines the number of clock cycles which pass before the first output data is valid within a read
burst access (counting from the clock edge where ADV was detected low). The number of inserted wait cycles
increases along with the input clock frequency. Please refer to
Table 11
for the proper setting.
Please note that the first access delay might be extended by another 1-3 wait cycles in case the burst read or write
access collides with an ongoing self-refresh operation.
Latency Modes
Figure 11
Latency Mode - Functional Diagram
Table 11
Latency Mode
Latency Mode Configuration
Max. Input Clock Frequency [MHz]
-12.5
reserved
reserved
50
80
-9.6
reserved
reserved
66
104
-15
reserved
reserved
40
66
0
1
2
3
Don't Care
DQx
Control
Read
N
CLK
NOP
NOP
NOP
Q
N+1
Q
N+2
Q
N+3
NOP
Q
N+4
NOP
Q
N+5
NOP
Q
N+6
NOP
Q
N+7
DQx
Q
N+1
Q
N+2
Q
N+3
Q
N+4
Q
N+5
Q
N+6
Q
N+7
DQx
Q
N+1
Q
N+2
Q
N+3
Q
N+4
Q
N+5
Q
N+6
Q
N+7
code0 (reserved)
code1 (reserved)
code2
code3
DQx
Q
N+1
Q
N+2
Q
N+3
Q
N+4
Q
N+5
Q
N+6
Q
N+7
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