參數(shù)資料
型號: HYS 64V32220GCDL
廠商: SIEMENS AG
英文描述: 3.3V SDRAM Modules(3.3V SDRAM 模塊)
中文描述: 3.3V的內(nèi)存模塊(3.3V的內(nèi)存模塊)
文件頁數(shù): 12/16頁
文件大小: 100K
代理商: HYS 64V32220GCDL
HYS64V32220GCDL
144 pin SO-DIMM SDRAM Modules
Infineon Technologies
12
12.99
T
SPD-Table for PC133 3-3-3 SO-DIMM Modules:
Byte#
Description
SPD Entry
Value
Hex
32Mx64
-7.5
80
08
04
0C
0
1
2
3
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses
(without BS)
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from Clock at
CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
128
256
SDRAM
4
5
6
7
8
9
10
02
40
00
01
75
54
1 / 2
64
0
LVTTL
7.5 ns
5.4 ns
10
11
12
none
00
80
Self-Refresh,
15.6
μ
s
x16
n/a / x8
t
ccd
= 1 CLK
13
14
15
SDRAM width, Primary
Error Checking SDRAM data width
Minimum clock delay for back-to-
back random column address
Burst Length supported
10
00
01
16
1, 2, 4, 8 & full
page
2
2, & 3
CS latency = 0
Write latency =
0
non buffered/
non reg.
Vcc tol +/-
10%
10.0 ns
6.0 ns
8F
17
18
19
20
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
04
06
01
01
21
SDRAM DIMM module attributes
00
22
SDRAM Device Attributes :General
0E
23
24
SDRAM Cycle Time at CL = 2
SDRAM Access Time from Clock at
CL=2
SDRAM Cycle Time at CL = 1
SDRAM Access Time from Clock at
CL=1
Minimum Row Precharge Time
A0
60
25
26
not supported
not supported
FF
FF
27
20 ns
14
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