參數(shù)資料
型號: HYS 64V4200GDL
廠商: SIEMENS AG
英文描述: 3.3 V SDRAM Modules(3.3 V 同步動態(tài)RAM模塊)
中文描述: 3.3伏內(nèi)存模塊(3.3伏同步動態(tài)內(nèi)存模塊)
文件頁數(shù): 7/15頁
文件大?。?/td> 126K
代理商: HYS 64V4200GDL
HYS 64V4200GDL/HYS 64V8220GDL
144-pin SO-DIMM SDRAM Modules
Data Book
7
12.99
Notes
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -
7.5 parts, 100 MHz for -8 parts, and at 66 MHz for -10 parts. Input signals are changed once
during
t
CK
, excepts for
I
CC6
and for standby currents when
t
CK
= infinity.
2. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 are assumed and the
V
DDQ
current is excluded.
Operating Currents per Memory Bank
T
A
= 0 to 70
°
C,
V
DD
= 3.3 V
±
0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Test Condition Symbol
-7.5 -8
Unit
Note
Operating current
t
RC
=
t
RC(MIN.)
,
t
CK
=
t
CK(MIN.)
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner to
maximize gapless data access
I
CC1
560 520 mA
1)
Precharge stand-by current
in Power Down Mode
CS =
V
IH(MIN.)
, CKE
V
IL(MAX.)
Precharge Stand-by Current
in Non-Power Down Mode
t
CK
= min.
t
CK
= infinity
I
CC2P
I
CC2PS
8
8
mA
1)
4
4
mA
1)
CS =
V
IH (MIN.)
, CKE
V
IH(MIN.)
No operating current
t
CK
= min.
t
CK
= infinity
I
CC2N
I
CC2NS
160 140 mA
1)
20
20
mA
1)
t
CK
= min., CS =
V
IH(MIN.)
,
active state (max. 4 banks)
CKE
V
IH(MIN.)
CKE
V
IL(MAX.)
I
CC3N
I
CC3P
200 180 mA
1)
32
32
mA
1)
Burst operating current
t
CK
= min.,
Read command cycling
I
CC4
440 400 mA
1), 2)
Auto refresh current
t
CK
= min.,
Auto Refresh command cycling
I
CC5
560 520 mA
1)
Self refresh current
Self Refresh Mode, CKE = 0.2 V
L-version
I
CC6
2
2
mA
1)
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