參數(shù)資料
型號(hào)： IA88C00-PLC68I-R-01
廠商： Innovasic Semiconductor
文件頁(yè)數(shù)： 20/80頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8BIT 20MHZ 68PLCC
標(biāo)準(zhǔn)包裝： 285
芯體尺寸： 8-位
速度： 20MHz
連通性： EBI/EMI，UART/USART
外圍設(shè)備： DMA，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類型： 外部程序存儲(chǔ)器
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 管件
IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright 2005
ENG 21 0 050519-00
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 27 of 80
1.888.824.4184
Figure 21. Counter 0 Mode, R224
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
X
0
Read/Write
R/W
D0 - When this bit is set to 1, the counter/timer is enabled. Operation begins on the rising edge of the first
processor clock period following the setting of this bit from a previously cleared value. Writing a 1 in this
field when the previous value was 1 has no effect on the operation of the counter/timer. When this bit is
cleared to 0, the counter/timer performs no operation during the next (and subsequent) processor clock
periods. A hardware reset forces this bit to 0.
Both counters are clocked by the rising edge of the incoming signal on P26 or p36 after the counter is
enabled. The maximum frequency of the external clock signal applied to P36 (or P26) equals the
maximum Xtal frequency divided by 4. The maximum gauaranteed Xtal frequency is 20 MHz, which
implies a maximum counter frequency of 5 MHz.
D1 - Reset/End of Count Status - This bit is set to 1 each time the counter reaches 0. Writing a 1 to this
bit resets it, while writing a 0 has no effect.
D2 - Zero Count Interrupt Enable - When this bit is set to 1, the counter/timer generates an interrupt
request when it counts to 0. A hardware reset forces this bit to 0.
D3 - Software Capture - When this bit is set to 1, the current counter value is loaded into the capture
register. This bit is automatically cleared following the capture.
D4 - Software Trigger - This bit is effectively "ORed" with the external rising-edge trigger input and can
be used by the software to force a trigger signal. This bit produces a trigger signal regardless of the setting
of the Input Pin Assignment field of the Mode register. This bit is automatically cleared following the
trigger.
D5 - Load Counter - The contents of the Time Constant register are transferred to the Counter prescaler
one clock period after this bit is set. This operation alone does not start the counter. This bit is
automatically cleared following the load.
D6 - Count Up/Down - This bit determines the count direction if internal up/down control is specified in
the Mode register. 1 indicates up; 0 indicates down.
D7 - Continuous/Single Cycle - When this bit is set to 1, the counter is reloaded with the time-constant
value when the counter reaches the end of the terminal count. The terminal count for down counting is
0000, while the one for up counting is FFFF. When this bit is cleared to 0, no reloading occurs.
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