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參數(shù)資料
| 型號： | IA88C00-PLC68I-R-01 |
| 廠商： | Innovasic Semiconductor |
| 文件頁數(shù)： | 54/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 20MHZ 68PLCC |
| 標(biāo)準(zhǔn)包裝： | 285 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | EBI/EMI，UART/USART |
| 外圍設(shè)備： | DMA，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | 外部程序存儲器 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 包裝： | 管件 |
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IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright 2005
ENG21 1 030617-04
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 58 of 80
1.888.824.4184
Interrupt Programming Model
The IA88C00 maintains program compatibility with the Super8. Enabling or disabling of interrupts are
controlled via the following registers:
Interrupt enable/disable. See the System Mode register (R222).
Level enable. See the interrupt Mask register (R221).
Level priority. See the Interrupt Priority register (R255, Bank 0).
Source enable/disable. Interrupt sources are enabled or disabled in the individual source’s Mode and
Control register.
Functional Overview
For an interrupt to be serviced, it’s source must be enabled. The corresponding interrupt and level must
likewise be enabled. Each interrupt input is conditioned with edge-triggered devices to convert all
interrupt inputs to “l(fā)evels”. The eliminates the requirement for external hardware to maintain the interrupt
input prior to servicing.
When an interrupt source is received the processor is “vectored” to the vector address associated with the
interrupt. In the fact of multiple interrupts, the enabled interrupt whose level has the highest priority is
serviced first. For interrupts within the same level, the priority of the individual interrupt takes
precedence.
Upon servicing the interrupt, the processor clears the Interrupt Enable bit in the System Mode register to
prevent a high priority interrupt from disrupting the service routine. The program counter and status flags
are pushed onto the stack and the program counter is loaded with the appropriate interrupt vector and the
interrupt service routine (ISR) begins to the execute. Upon completion, the ISR executes an RET
instruction. The flags and program counter are popped off the stack and the Interrupt Enable bit in the
System Mode register is set.
The IA88C00 supports a special mode of “fast” interrupt processing. Utilization of this mode requires
program intervention. The vector address of the ISR must be loaded into the instruction pointer and the
Fast Interrupt enable bit in the System Mode Register must be set. Upon receipt of the interrupt source,
the ISR vector is loaded into the program counter while the old value of the program counter is saved in
the Instruction Pointer. Status flags are saved in the FLAGs register and the Fast interrupt Status Bit in
FLAGS is set. Upon completion of the ISR, the process is reversed.
Stack Operation
The IA88C00 maintains program model compatibility on all Stack operations. The stack may be
maintained in either the register file or in data memory space. For programming model details see
registers R216/R217 (the stack pointer) and register R254 (Memory Timing register)
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