參數(shù)資料
型號(hào)： IA88C00-PLC68I-R-01
廠(chǎng)商： Innovasic Semiconductor
文件頁(yè)數(shù)： 37/80頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8BIT 20MHZ 68PLCC
標(biāo)準(zhǔn)包裝： 285
芯體尺寸： 8-位
速度： 20MHz
連通性： EBI/EMI，UART/USART
外圍設(shè)備： DMA，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類(lèi)型： 外部程序存儲(chǔ)器
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線(xiàn)）
包裝： 管件
IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright 2005
ENG 21 0 050519-00
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 42 of 80
1.888.824.4184
Figure 45. Port 2/3 A Interrupt Pending Register (P2AIP), R252 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
0
Read/Write
?
Read Only (writeable for reset puposes)
The Port 2/3 A Interrupt Pending and Port 2/3 B Interrupt Pending registers represent the software
interface to the negative edge-triggered flip-flops associated with external interrupt inputs. Each bit of
these registers corresponds to an interrupt generated by an external source. When one of these registers is
read, the value of each bit represents the state of the corresponding interrupt. When one of these registers
is written to, a 1 in a bit position causes the corresponding edge-triggered flip-flop to be reset to 0. A 0
causes no action.
The software interfaces with these registers to poll the interrupts and also to reset pending interrupts as
they are processed. Figure 45 shows the pin relationship.
Figure 46. Port 2/3 B Interrupt Pending Register (P2BIP), R253 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
0
Read/Write
?
Read Only (writeable for reset puposes)
The Port 2/3 A Interrupt Pending and Port 2/3 B Interrupt Pending registers represent the software
interface to the negative edge-triggered flip-flops associated with external interrupt inputs. Each bit of
these registers corresponds to an interrupt generated by an external source. When one of these registers is
read, the value of each bit represents the state of the corresponding interrupt. When one of these registers
is written to, a 1 in a bit position causes the corresponding edge-triggered flip-flop to be reset to 0. A 0
causes no action.
The software interfaces with these registers to poll the interrupts and also to reset pending interrupts as
they are processed. Figure 46 shows the pin relationship.
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