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參數(shù)資料
| 型號(hào)： | IBM25PPC750-DB0M2500 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 3/42頁 |
| 文件大?。?/td> | 496K |
| 代理商： | IBM25PPC750-DB0M2500 |
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7/15/99
v 3.2
Datasheet
Page 11
Preliminary Copy
PowerPC 750TM SCM RISC Microprocessor
60x Bus Input AC Specications
Table 8 provides the 60X bus input AC timing specifications for the 750 as defined in Figure 10and Figure 11.
Input timing specifications for the L2 bus are provided in Section, “L2 Bus Input AC Specifications” on page
Figure 9. SYSCLK Input Timing Diagram
Table 8.
60X Bus Input Timing Specications1
See Table 2 for operating conditions.
Num
Characteristic
200, 225, 233, 250,
266, 275 MHz
300 MHz
Unit
Notes
Min
Max
Min
Max
10a
Address/Data/Transfer Attribute Inputs Valid to
SYSCLK (Input Setup)
2.5
—
2.5
—
ns
2
10b
All Other Inputs Valid to SYSCLK (Input Setup)
3.0
—
2.5
—
ns
3
10c
Mode Select Input Setup to HRESET
(DRTRY,TLBISYNC)
8
—8—
tSYSCLK
4,5,6,7
11a
SYSCLK to Address/Data/Transfer Attribute
Inputs Invalid (Input Hold)
1.0
—
0.8
—
ns
2
11b
SYSCLK to All Other Inputs Invalid (Input Hold)
1.0
—
0.8
—
ns
3
11c
HRESET to mode select input hold
(DRTRY, TLBISYNC)
0
—
0
—
ns
4,6,7
Note:
1. Input specications are measured from the TTL level (0.8 to 2.0V) of the signal in question to the 1.4V of the rising
edge of the input SYSCLK. Input and output timings are measured at the pin (see Figure 10
2. Address/Data Transfer Attribute inputs are composed of the following: A[0-31], AP[0-3], TT[0-4],TBST, TSIZ[0-2],
GBL, DH[0-31), DL[0-31], DP[0-7].
3. All other signal inputs are composed of the following: TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY,
TEA, DBDIS, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 11).
5. tSYSCLK, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be
multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specication is for conguration mode select only. Also note that the HRESET must be held asserted for a mini-
mum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence.
VM
CVIL
CVIH
VM = Midpoint Voltage (1.4V)
1
4
SYSCLK
4
2
3
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