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| 型號(hào)： | IBM25PPC750-DB0M2500 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 42/42頁 |
| 文件大?。?/td> | 496K |
| 代理商： | IBM25PPC750-DB0M2500 |
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7/15/99
v 3.2
Datasheet
Page 9
Preliminary Copy
PowerPC 750TM SCM RISC Microprocessor
Table 6 provides the power consumption for the 750.
Table 5.
DC Electrical Specications
See Table 2 for operating conditions
.
Characteristic
Symbol
Min
Max
Unit
Notes
Input high voltage (all inputs except SYSCLK)
VIH
2.0
3.465
V
1,2
Input low voltage (all inputs except SYSCLK)
VIL
GND
0.8
V
SYSCLK input high voltage
CVIH
2.4
OVDD
V1
SYSCLK input low voltage
CVIL
GND
0.4
V
Input leakage current, VIN = OVDD
Iin
—30
A
1,2
Hi-Z (off state) leakage current, VIN = OVDD
ITSI
—30
A
1,2
Output high voltage, IOH = –6mA
VOH
2.4
—
V
Output low voltage, IOL = 6mA
VOL
—
0.4
V
Capacitance, VIN =0V, f = 1MHz
Cin
—
5.0
pF
2,3
Note:
1. For 60x bus signals, the reference is OVDD, while L2OVDD is the reference for the L2 bus signals.
2. Excludes test signals LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and IEEE 1149.1 signals.
3. Capacitance values are guaranteed by design and characterization, and are not tested.
Table 6.
Power Consumption
See Table 2 for operating conditions
.
Processor CPU Frequency
Unit
Notes
200 MHz
225/233 MHz
250/266 MHz
275 MHz
300 MHz
Full-On Mode
Typical
Maximum
4.7
5.6
6.5
6.7
7.3
W
1,3,4,5
7.5
8.8
9.8
10.1
11.0
W
1,2,4,5
Doze Mode
Maximum
1.6
1.8
2.1
2.2
2.3
W
1,2,5
Nap Mode
Maximum
250
mW
1,2,5
Sleep Mode
Maximum
100
mW
1,2,5
Note:
1. These values apply for all valid 60x bus and L2 bus ratios. The values do not include I/O Supply Power (OVDD and
L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but is typically
<10% of VDD power. Worst case power consumption for AVDD = 15mW and L2AVDD = 15mW.
2. Maximum power is measured at VDD = 2.75.
3. Typical power is an average value measured at VDD = AVDD = L2AVDD = 2.7V, OVDD = L2OVDD= 3.3V in a system execut-
ing typical applications and benchmark sequences.
4. Full-on mode uses a worst case instruction mix.
5. Guaranteed by design and characterization, and is not tested.
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