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參數(shù)資料
| 型號： | IBM25PPC750-DB0M2500 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 5/42頁 |
| 文件大?。?/td> | 496K |
| 代理商： | IBM25PPC750-DB0M2500 |
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7/15/99
v 3.2
Datasheet
Page 13
Preliminary Copy
PowerPC 750TM SCM RISC Microprocessor
60x Bus Output AC Specications
Table 9 provides the 60x bus output AC timing specifications for the 750 as defined in Figure 12. Output tim-
ing specification for the L2 bus are provided in Section “L2 Bus Output AC Specifications.”
Table 9.
60X Bus Output AC Timing Specications1
See Table 2 for operating conditions, CL = 50pF
2
Num
Characteristic
200, 225, 233, 250,
266, 275 MHz
300 MHz
Unit
Notes
Min
Max
Min
Max
12
SYSCLK to Output Driven
(Output Enable Time)
0.5
—
0.5
—
ns
13
SYSCLK to Output Valid (TS, ABB, ARTRY, and
DBB)
—
6.5
—
6.0
ns
5
14
SYSCLK to all other Output Valid (all except TS,
ABB, ARTRY, and DBB)
—
6.5
—
6.0
ns
5
15
SYSCLK to Output Invalid (Output Hold)
1.0
—
0.8
—
ns
3
16
SYSCLK to Output High Impedance (all signals
except ABB, ARTRY, and DBB)
—
6.0
—
6.0
ns
8
17
SYSCLK to ABB and DBB high impedance after pre-
charge
—
1.0
—
1.0
tSYSCLK
4,6,8
18
SYSCLK to ARTRY high impedance before pre-
charge
—
5.5
—
5.5
ns
8
19
SYSCLK to ARTRY precharge enable
0.2 x
tSYSCLK +
1.0
—
0.2 x
tSYSCLK +
1.0
—
ns
3,4,7
20
Maximum delay to ARTRY precharge
—1—1
tSYSCLK
4,7
21
SYSCLK to ARTRY high impedance after precharge
—2—2
tSYSCLK
4,7,8
Note:
1. All output specications are measured from the 1.4V of the rising edge of SYSCLK to the TTL level (0.8V or 2.0V) of the
signal in question. Both input and output timings are measured at the pin.
2. All maximum timing specications assume CL = 50pF.
3. This minimum parameter assumes CL = 0pF.
4. tSYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be
multiplied by the period of SYSCLK to compute the actual time duration of the parameter in question.
5. Output signal transitions from GND to 2.0V or OVDD to 0.8V.
6. Nominal precharge width for ABB and DBB is 0.5 tSYSCLK.
7. Nominal precharge width for ARTRY is 1.0 tSYSCLK.
8. Guaranteed by design and characterization, and not tested.
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|---|---|
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