參數(shù)資料
型號： ICS1893AFILF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 100/136頁
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝： 30
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 管件
其它名稱： 1893AFILF
ICS1893AF, Rev D 10/26/04
October, 2004
66
Chapter 8
Management Register Set
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.3.9
Remote Fault (bit 1.4)
An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893AF sets bit 1.4 based on the
Remote Fault bit received from its remote link partner. The ICS1893AF receives the Remote Fault bit as
part of the Link Code Word exchanged during the auto-negotiation process. If the ICS1893AF receives a
Link Code Word from its remote link partner and the Remote Fault bit is set to:
Zero, then the ICS1893AF sets bit 1.4 to logic zero.
One, then the ICS1893AF sets bit 1.4 to logic one. In this case, the remote link partner is reporting the
detection of a fault, which typically occurs when the remote link partner is having a problem with its
receive channel.
Bit 1.4 is a latching high status bit. (For more information on latching high and latching low bits, see Section
Note:
The ICS1893AF has two versions of the Remote Fault bit.
One version of the Remote Fault bit is a latching high version. An STA can access this version
through either Management Register 1 (bit 1.4) or 17 (bit 17.1). This bit 1.4/17.1 is cleared when
an STA reads either of these registers. (Bit 1.4 is identical to bit 17.1 in that they are the same
internal bit.)
Another version of the Remote Fault bit is updated whenever the ICS1893AF receives a new
Link Control Word. An STA can access this version through Management Register 5 (bit 5.13),
which like bits 1.4/17.1, also reports the status of the Remote Fault bit received from the remote
link partner. However, bit 5.13 is not a latching high bit.
The operation of both bit 1.4/17.1 and bit 5.13 are in compliance with the IEEE Std 802.3u.
8.3.10
Auto-Negotiation Ability (bit 1.3)
The STA reads bit 1.3 to determine if the ICS1893AF can support the auto-negotiation process. If the
ICS1893AF:
Cannot support the auto-negotiation process, it clears bit 1.3 to logic zero.
Can support the auto-negotiation process, it sets bit 1.3 to logic one. (For the ICS1893AF, the default
value of bit 1.3 is logic one.)
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參數(shù)描述
ICS1893AFILFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893AFIT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AFLF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):1/1 規(guī)程:RS422，RS485 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 其它名稱:ISL31470EIBZ-T7ACT
ICS1893AFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893AFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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