參數(shù)資料
型號： ICS1893AFILF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 96/136頁
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝： 30
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 管件
其它名稱： 1893AFILF
ICS1893AF, Rev D 10/26/04
October, 2004
62
Chapter 8
Management Register Set
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.2.8
Duplex Mode (bit 0.8)
This bit provides a means of controlling the ICS1893AF Duplex Mode. Its operation depends on several
other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the
ICS1893AF is configured for:
Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893AF isolates bit 0.8 and uses the
DPXSEL input pin to establish the Duplex mode for the ICS1893AF. In this Hardware mode:
– Bit 0.8 is undefined.
– The ICS1893AF provides a Duplex Mode Status bit (in the QuickPoll Detailed Status Register, bit
17.14), which always shows the setting of an active link.
Software mode (that is, the HW/SW pin is logic one), the function of bit 0.8 depends on the
Auto-Negotiation Enable bit, 0.12. When the auto-negotiation process is:
– Enabled, the ICS1893AF isolates bit 0.8 and relies upon the results of the auto-negotiation process
to establish the duplex mode.
– Disabled, bit 0.8 determines the Duplex mode. Setting bit 0.8 to logic:
Zero selects half-duplex operations.
One selects full-duplex operations. (When the ICS1893AF is operating in Loopback mode, it
isolates bit 0.8, which has no effect on the operation of the ICS1893AF.)
8.2.9
Collision Test (bit 0.7)
This bit controls the ICS1893AF Collision Test function. When an STA sets bit 0.7 to logic:
Zero, the ICS1893AF disables the collision detection circuitry for the Collision Test function. In this case,
the COL signal does not track the TXEN signal. (The default value for this bit is logic zero, that is,
disabled.)
One, as per the ISO/IEE 8802-3 standard, clause 22.2.4.1.9, the ICS1893AF enables the collision
detection circuitry for the Collision Test function, even if the ICS1893AF is in Loopback mode (that is, bit
0.14 is set to 1). In this case, the Collision Test function tracks the Collision Detect signal (COL) in
response to the TXEN signal. The ICS1893AF asserts the Collision signal (COL) within 512 bit times of
receiving an asserted TXEN signal, and it de-asserts COL within 4 bit times of the de-assertion of the
TXEN signal.
8.2.10
IEEE Reserved Bits (bits 0.6:0)
The IEEE reserves these bits for future use. When an STA:
Reads a reserved bit, the ICS1893AF returns a logic zero.
Writes to a reserved bit, it must use the default value specified in this data sheet.
The ICS1893AF uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the
ICS1893AF, an STA must maintain the default value of these bits. Therefore, ICS recommends that during
any STA write operation, an STA write the default value to all reserved bits, even those bits that are Read
Only.
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ICS1893AFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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