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參數(shù)資料
| 型號(hào)： | ICS1893AFILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 67/136頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 1893AFILF |
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ICS1893AF, Rev D 10/26/04
October, 2004
36
Chapter 7
Functional Blocks
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
7.2.1
Auto-Negotiation General Process
The Auto-Negotiation sublayer uses a physical signaling technique that is transparent at the packet level
and all higher protocol levels. This technique builds on the link pulse mechanism employed in 10Base-T
operations and is fully compliant with clause 28 of the ISO/IEC 8802-3 standard.
During the auto-negotiation process, both the ICS1893AF and its remote link partner use Fast Link Pulses
(FLPs) to simultaneously ‘a(chǎn)dvertise’ (that is, exchange) information on their respective technology
capabilities as follows:
1.
For the auto-negotiation process to take place, both the ICS1893AF and its remote link partner must
first both support and be enabled for Auto-Negotiation.
2.
The ICS1893AF obtains the data for its FLP bursts from the Auto-Negotiation Advertisement Register
(Register 4).
3.
Both the ICS1893AF and the remote link partner substitute Fast Link Pulse (FLP) bursts in place of the
Normal Link Pulses (NLPs). In each FLP burst, the ICS1893AF transmits information on its technology
capability through its Link Control Word, which includes link configuration and status data.
4.
Similarly, the ICS1893AF places the Auto-Negotiation data received from its remote link partner's FLP
bursts into the Auto-Negotiation Link Partner Ability Register (Register 5).
5.
After the ICS1893AF and its remote link partner exchange technology capability information, the
ICS1893AF Auto-Negotiation sublayer contrasts the data in Registers 4 and 5 and automatically
selects for the operating mode the highest-priority technology that both Register 4 and 5 have in
common. (That is, both the ICS1893AF and its remote link partner use a predetermined priority list for
selecting the operating mode, thereby ensuring that both sides of the link make the same selection.) As
follows from Annex 28B of the ISO/IEC 8802-3 standard, the pre-determined technology priorities are
listed from 1 (highest priority) to 5 (lowest priority):
(1) 100Base-TX full duplex
(2) 100Base-T4. (The ICS1893AF does not support this technology.)
(3) 100Base-TX (half duplex)
(4) 10Base-T full duplex
(5) 10Base-T (half duplex)
Table 7-1 shows an example of how the selection process of the highest-priority technology takes
place.
6.
To indicate that the auto-negotiation process is complete, the ICS1893AF sets bits 1.5 and 17.4 high to
logic one. After successful completion of the auto-negotiation process, the ICS1893AF
Auto-Negotiation sublayer performs the following steps:
a. It sets to logic one the Status Register’s Auto-Negotiation Complete bit (bit 1.5, which is also
available in the QuickPoll register as bit 17.4).
b. It enables the negotiated link technology (such as the 100Base Transmit modules and 100Base
Receive modules).
c. It disables the unused technologies to reduce the overall power consumption.
Table 7-1.
Example of Selection Process of Highest-Priority Technology
If Register 4 Has These
Technologies:
If Register 5 Has These
Technologies:
Resulting Highest-Priority Common
Technology from Auto-Negotiation
Sublayer
(3) 100Base-TX half duplex
(1) 100Base-TX full duplex
(3) 100Base-TX half duplex
(4) 100Base-T full duplex
(3) 100Base-TX half duplex
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| ICS1893BFILF | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| ICS1894KI-32LF | PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894KI-40LFT | PHYCEIVER LOW PWR 3.3V 40QFN |
| ID82C55A | IC I/O EXPANDER 24B 40DIP |
| ID82C82 | IC DRIVER BUS OCT LATCHING 20DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893AFILFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893AFIT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AFLF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:RS422，RS485 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 其它名稱:ISL31470EIBZ-T7ACT |
| ICS1893AFLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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