- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1923 > ICS1893AFILF (IDT, Integrated Device Technology Inc)PHYCEIVER LOW PWR 3.3V 48-SSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS1893AFILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 75/136頁 |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 1893AFILF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁當(dāng)前第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁
Chapter 7
Functional Blocks
ICS1893AF, Rev. D 10/26/04
October, 2004
43
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
7.3.5
PCS Control Signal Generation
For the PCS sublayer, there are two control signals: a Carrier Sense signal (CRS) and a Collision Detect
signal (COL).
The CRS control signals is generated as follows:
1.
When a logic zero is detected in an idle bit stream, the Receive Functions examines the ensuing bits.
2.
When the Receive Functions find the first two non-contiguous zero bits, the Receive state machine
moves into the Carrier Detect state.
3.
As a result, the Boolean Receiving variable is set to TRUE.
4.
Consequently, the Carrier Sense state machine moves into the Carrier Sense ‘on’ state, which asserts
the CRS signal.
5.
If the PCS Functions:
a. Cannot confirm either the /I/J/ (IDLE, J) symbols or the /J/K/ symbols, the receive error signal
(RX_ER) is asserted, and the Receive state machine returns to the IDLE state. In IDLE, the
Boolean Receiving variable is set to FALSE, thereby causing the Carrier Sense state machine to
set the CRS signal to FALSE.
b. Can confirm the /I/J/K/ symbols, then the Receive state machine transitions to the ‘Receive’ state.
The COL control signal is generated by the transmit modules. For details, see Section 7.3.3.1, “PCS
7.3.6
4B/5B Encoding/Decoding
The 4B/5B encoding methodology maps each 4-bit nibble to a 5-bit symbol (also called a “code group”).
There are 32 five-bit symbols, which include the following:
Of the 32 five-bit symbols, 16 five-bit symbols are required to represent the 4-bit nibbles.
The remaining 16 five-bit symbols are available for control functions. The IEEE Standard defines 6
symbols for control, and the remaining 10 symbols of this grouping are invalid. The 6 control symbols
include the following:
– /H/, which represents a Halt, also used to signify a Transmit Error
– /I/, which represents an IDLE
– /J/, which represents the first symbol of the Start-of-Stream Delimiter (SSD)
– /K/, which represents the second symbol of the Start-of-Stream Delimiter (SSD)
– /T/, which represents the first symbol of the End-of-Stream Delimiter (ESD)
– /R/, which represents the second symbol of the End-of-Stream Delimiter (ESD)
If the ICS1893AF PCS receives:
– One of the 10 undefined symbols, it sets its QuickPoll Detailed Status Register’s Invalid Symbol bit
(bit 17.7) to logic one.
– A Halt symbol, it sets the Halt Symbol Detected bit in its QuickPoll Detailed Status Register (bit 17.6)
to logic one.
Note:
An STA can force the ICS1893AF to transmit symbols that are typically classified as invalid, by
both (1) setting the Extended Control Register’s Transmit Invalid Codes bit (bit 16.2) to logic one
and (2) asserting the associated TXER signal. For more information, see Section 8.11.7, “Invalid
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1893BFILF | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| ICS1894KI-32LF | PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894KI-40LFT | PHYCEIVER LOW PWR 3.3V 40QFN |
| ID82C55A | IC I/O EXPANDER 24B 40DIP |
| ID82C82 | IC DRIVER BUS OCT LATCHING 20DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893AFILFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893AFIT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AFLF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:RS422，RS485 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 其它名稱:ISL31470EIBZ-T7ACT |
| ICS1893AFLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。