參數(shù)資料
型號(hào)： ICS1894KI-40LFT
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 45/53頁(yè)
文件大小： 0K
描述： PHYCEIVER LOW PWR 3.3V 40QFN
標(biāo)準(zhǔn)包裝： 1
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII，RMII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-VFQFPN（6x6）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 800-2032-6
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
5
ICS1894-40
REV K 022412
Strapping Options
1. IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise.
2. IO/Ipd = Digital Input with internal 20k pull-down during power on reset/hardware reset; output pin otherwise.
3. If RXTRI/RXD1 pin is latched high during power on reset/hardware reset, P1/ISO/LED1 functions as RX real time
isolation control input after latch and LED1 function will be disabled.
Functional Description
The ICS1894-40 is an ethernet PHYceiver. During data
transmission, it accepts sequential nibbles/di-bits from the
MAC (Media Access Control), converts them into a serial bit
stream, encodes them, and transmits them over the medium
through an external isolation transformer. When receiving
data, the ICS1894-40 converts and decodes a serial bit
stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles/di-bits. It
subsequently presents these nibbles/di-bits to the MAC
Interface.
Pin
Number
Pin
Name
Pin
Type1
Pin Function
1
AMDIX
IN/Ipu
1 = AMDIX enable
0 = AMDIX disable
16
HWSW/CRS
IO/Ipd
Hardware pin select enable. Active during power-on and hardware reset.
17
REGPIN/COL
IO/Ipd
Full register access enable. Active during power-on and hardware reset.
18
AMDIX/RXD2
IO/Ipu
1 = AMDIX enable
0 = AMDIX disable
38
P4/LED2
IO/Ipu
The PHY address is set by P[4:0] at power-on reset. P0 and P1 must have external
pull-up or pull-down to set address at start up.
19
P3/RXD2
IO/Ipd
12
P2/INT
IO/Ipd
40
P1/ISO/LED1
IO/
39
P0/LED0
IO/
21
SI/LED4
IO/Ipd
MII/SI mode select. Active during power-on and hardware reset.
20
RXTRI/RXD1
IO/Ipd
1=Realtime receiver isolation enable3;
0=RX output enable
22
FDPX/RXD0
IO/Ipu
1=Full duplex
0=Half duplex
Ignored if Auto negotiation is enabled
23
RMII/RXDV
IO/Ipd
[1x]=RMII mode
[01]=SI mode (Serial interface mode)
[00]=MII mode
24
SPEED
IO/Ipu
1=100M mode
0=10M mode
26
ANSEL/RXCLK
IO/Ipu
1=Enable auto negotiation
0=Disable auto negotiation
27
NOD/RXER
IO/Ipd
0=Node mode
1=repeater mode
28
SPEED/TXCLK
IO/Ipu
1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
32
LED3
IO/Ipu
LED3 output
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