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參數(shù)資料
| 型號： | ICS93701YGT |
| 英文描述： | DDR Phase Lock Loop Clock Driver |
| 中文描述： | 復員鎖相環(huán)時鐘驅(qū)動器 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 184K |
| 代理商： | ICS93701YGT |
3
ICS93701
0417B—10/29/02
Byte 0: Output Control
(1= enable, 0 = disable)
T
7
6
5
4
3
2
1
0
I
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
#
0
3
2
N
I
P
,
2
,
2
D
W
1
1
1
1
1
1
1
1
P
N
O
I
T
P
I
C
C
R
K
K
C
L
L
S
C
C
d
d
d
d
d
d
E
D
,
T
,
T
v
s
v
s
v
s
v
s
v
s
v
s
8
9
K
K
L
L
e
e
e
e
e
e
C
C
R
R
R
R
R
R
6
-
-
-
-
-
-
e
e
e
e
e
e
Byte 1: Output Control
(1= enable, 0 = disable)
T
7
6
5
4
3
2
1
0
I
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
#
N
-
-
-
-
-
-
-
-
I
P
D
W
1
1
1
1
1
1
1
1
P
N
O
I
T
P
I
R
C
S
E
d
d
d
d
d
d
d
d
D
e
e
e
e
e
e
e
e
v
s
v
s
v
s
v
s
v
s
v
s
v
s
v
s
e
e
e
e
e
e
e
e
R
R
R
R
R
R
R
R
Byte 3: Reserved
(1= enable, 0 = disable)
T
7
6
5
4
3
2
1
0
I
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
#
N
-
-
-
-
-
-
-
-
I
P
D
W
1
1
1
1
1
1
1
1
P
N
O
I
T
P
I
R
C
S
E
d
d
d
d
d
d
d
d
D
e
e
e
e
e
e
e
e
v
s
v
s
v
s
v
s
v
s
v
s
v
s
v
s
e
e
e
e
e
e
e
e
R
R
R
R
R
R
R
R
Byte 4: Reserved
(1= enable, 0 = disable)
Byte 2: Reserved
(1= enable, 0 = disable)
T
7
6
5
4
3
2
1
0
I
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
#
N
-
-
-
-
-
-
-
-
I
P
D
W
1
1
1
1
1
1
1
1
P
N
O
I
T
P
I
R
C
S
E
d
d
d
d
d
d
d
d
D
e
e
e
e
e
e
e
e
v
s
v
s
v
s
v
s
v
s
v
s
v
s
v
s
e
e
e
e
e
e
e
e
R
R
R
R
R
R
R
R
T
I
B
B
B
B
B
B
B
B
B
#
N
-
-
-
-
-
-
-
-
I
P
D
W
0
0
0
0
0
1
1
0
P
N
O
I
T
)
)
)
)
)
)
)
)
P
I
R
e
N
e
N
e
N
e
N
e
N
e
N
e
N
e
N
C
(
(
(
(
(
(
(
(
S
d
d
d
d
d
d
d
d
E
e
e
e
e
e
e
e
e
D
7
6
5
4
3
2
1
0
v
e
v
e
v
e
v
e
v
e
v
e
v
e
v
e
s
s
s
s
s
s
s
s
e
e
e
e
e
e
e
e
R
R
R
R
R
R
R
R
Byte 5: Reserved
(1= enable, 0 = disable)
Note: Don’t write into this register, writing into this
register can cause malfunction
T
7
6
5
4
3
2
1
0
I
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
#
N
I
P
,
,
,
1
,
2
,
2
,
4
,
4
,
3
D
W
1
1
1
1
1
1
1
1
P
N
O
I
T
P
I
C
C
C
C
C
C
C
C
R
K
K
K
K
K
K
K
K
C
L
L
L
L
L
L
L
L
S
C
C
C
C
C
C
C
C
E
D
,
T
,
T
,
T
,
T
,
T
,
T
,
T
,
T
2
6
0
1
2
3
4
5
6
7
K
K
K
K
K
K
K
K
L
L
L
L
L
L
L
L
C
C
C
C
C
C
C
C
9
9
1
2
4
4
4
3
7
3
0
相關PDF資料 |
PDF描述 |
|---|---|
| ICS93705 | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712YF-PPP-T | 2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 2 DIMM DDR Fanout Buffer |
| ICS93712 | 2 DIMM DDR Fanout Buffer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS93705 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712 | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-PPP-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
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