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參數(shù)資料
| 型號： | ICS93701YGT |
| 英文描述： | DDR Phase Lock Loop Clock Driver |
| 中文描述： | 復員鎖相環(huán)時鐘驅動器 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 184K |
| 代理商： | ICS93701YGT |
4
ICS93701
0417B—10/29/02
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+ 0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output Parameters
T
A
= 0 - 85
o
C; Supply Voltage A
VDD
, V
DD
= 2.5V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
Input High Current
I
IH
Input Low Current
I
IL
I
DD2.5
CL = 0pF @ 100MHz
I
DDPD
CL = 0pF @ 100MHz
Output High Current
I
OH
V
DD
= 2.3V, V
OUT
= 1V
Output Low Current
I
OL
V
DD
= 2.3V, V
OUT
= 1.2V
High Impedance Output
Current
CONDITIONS
V
IN
= V
DD
or GND
V
IN
= V
DD
or GND
MIN
5
TYP
MAX
UNITS
μA
μA
mA
mA
mA
mA
5
185
0.15
-32
35
210
100
-18
26
Input Clamp Voltage
V
IK
V
DDQ
= 2.3V I
IN
= -18mA
V
DD
= min to max,
I
OH
= -1 mA
V
DDQ
= 2.3V,
I
OH
= -12 mA
V
DD
= min to max
I
OL
=1 mA
V
DDQ
= 2.3 V
I
OL
=12 mA
V
IN
= GND or V
DD
V
OUT
= GND or V
DD
-1.2
V
Input Capacitance
1
Output Capacitance
1
1
Guaranteed by design, not 100% tested in production.
C
IN
C
OUT
3
3
pF
pF
Operating Supply
Current
I
OZ
V
DD
=2.7V, V
OUT
=V
DD
or GND
0.1
±10
μA
0.6
V
OL
Low-level output voltage
High-level output voltage
V
OH
V
DDQ
- 0.1
1.7
V
V
0.05
2.45
V
V
0.35
0.1
2.10
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相關代理商/技術參數(shù) |
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|---|---|
| ICS93705 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712 | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-PPP-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
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