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參數(shù)資料
| 型號： | ICS93701YGT |
| 英文描述： | DDR Phase Lock Loop Clock Driver |
| 中文描述： | 復(fù)員鎖相環(huán)時鐘驅(qū)動器 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 184K |
| 代理商： | ICS93701YGT |
6
ICS93701
0417B—10/29/02
Switching Characteristics
PARAMETER
Low-to high level
propagation delay time
High-to low level
propagation delay time
Output enable time
Output disable time
Period Jitter
Half-period jitter
Cycle to Cycle Jitter1
Phase error
Output to Output Skew
Pulse skew
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
t
EN
tdis
PD# to any output
PD# to any output
100/133/166MHz
100/133/166MHz
100/133/166MHz
100/133/166Mhz
3
3
ns
ns
ps
ps
ps
ps
ps
ps
%
%
%
ps
-40
-120
±25
±50
30
-100
60
60
50
49
49
1.9
40
100
65
150
100
100
50.5
50
50
2
t(jit_hper)
T
cyc-
T
cyc
t
(phase error)
T
skew
T
skewp
-150
66MHz to 100MHz
101MHz to 133MHz
135MHz to 167MHz
Load = 120
/14pF
49.5
48.5
48.5
1
Slew Rate
t
SLEW
Notes:
1. Refers to transition on noninverting outputs in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
high frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, where the cycle (t
c
)
decreases as the frequency goes up.
Duty cycle
DC
2
3.5
t
PHL
1
CLK_IN to any output
3.5
t
PLH
1
CLK_IN to any output
ns
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS93705 | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712YF-PPP-T | 2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 2 DIMM DDR Fanout Buffer |
| ICS93712 | 2 DIMM DDR Fanout Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS93705 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712 | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-PPP-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
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