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參數(shù)資料
| 型號(hào)： | ICS93701YGT |
| 英文描述： | DDR Phase Lock Loop Clock Driver |
| 中文描述： | 復(fù)員鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 184K |
| 代理商： | ICS93701YGT |
5
ICS93701
0417B—10/29/02
Recommended Operating Condition
(see note1)
T
A
= 0 - 85
o
C; Supply Voltage A
VDD
, V
DD
= 2.5V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
V
DDQ
, A
VDD
V
DDI2C
V
IL
V
IH
Input differential-pair
voltage swing
1
Input differential crossing
voltage
CONDITIONS
MIN
2.3
2.3
-0.3
0.4
0.36
0.5
TYP
2.5
MAX
2.7
3.6
V
DD
-0.4
V
DD
+0.3
V
DDQ
+0.6
V
DDQ
+0.6
UNITS
V
V
V
V
V
0
0.71
DC - CLKT, FB_INT
AC - CLKT, FB_INT
Output differential crossing
voltage
1
Differential input signal voltage specifies the differential voltage [V
TR
- V
CP
] required for switching,
where V
TR
is the true input level and V
CP
is the complementary input level.
V
OX
V
DDQ
/2 -0.2
1.25
V
DDQ
/2 +0.2
V
Input voltage level
Analog/core Supply
Voltage
V
ID
V
V
IX
0.45x(V
IH
-V
IL
)
0.55x(V
IH
-V
IL
)
Timing Requirements
T
A
= 0 - 85
o
C; Supply Voltage A
VDD
, V
DD
= 2.5V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
Max clock frequency
freq
op
Application Frequency Range
freq
App
Input clock duty cycle
d
tin
CONDITIONS
2.5V+0.2V @ 25
o
C
2.5V+0.2V @ 25
o
C
MIN
33
60
40
MAX
270
170
60
UNITS
MHz
MHz
%
from V
DD
= 3.3V to 1%
target freq.
100
μs
CLK stabilization
T
STAB
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|---|---|
| ICS93705 | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712YF-PPP-T | 2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 2 DIMM DDR Fanout Buffer |
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|---|---|
| ICS93705 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712 | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-PPP-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
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