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參數(shù)資料
| 型號： | ICSSSTUA32S869B |
| 英文描述： | 14-Bit Configurable Registered Buffer for DDR2 |
| 中文描述： | 14位可配置的注冊緩沖DDR2內(nèi)存 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ICSSSTUA32S869B |
11
ICSSSTUA32S869B
Advance Information
1173—10/28/05
Electrical Characteristics - DC
T
A
= 0 - 70°C; V
DD
= 2.5 +/-0.2V, V
DDQ
=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
V
IK
I
I
= -18mA
I
OH
= -100μA
I
OH
= 6mA
I
OL
= 100μA
I
OL
= 6mA
I
I
All Inputs
V
I
= V
DD
or GND
Standby (Static)
RESET# = GND
V
I
= V
IH(AC)
or V
IL(AC)
,
RESET# = V
DD
RESET# = V
DD
,
V
I
= V
IH(AC)
or V
IL(AC)
,
CLK and CLK# switching
50% duty cycle.
RESET# = V
DD
,
V
I
= V
IH(AC)
or V
IL (AC)
,
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
Input capacitance,
D
n
, PAR_IN inputs
Input capacitance,
DCS#
n
Input capacitance,
CK and CK# inputs
2
Input capacitance,
RESET# input
Data Inputs
CLK and CLK#
RESET#
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - The vendor must supply this value for full device description.
V
DDQ
MIN
TYP
MAX
-1.2
UNITS
1.7V
1.7V
1.7V
1.7V
1.9V
V
DDQ
- 0.2
1.2
0.2
0.5
±5
0.2
μA
μA
Operating (Static)
TBD
mA
Dynamic operating
(clock only)
TBD
μ/clock
MHz
Dynamic Operating
(per each data input)
TBD
μA/ clock
MHz/data
V
I
= V
REF
± 250 mV
2.5
3.5
pF
2
3
pF
2
3
pF
V
I
= V
DD
or GND
Note 2
Note 2
pF
2.5
2
3.5
3
2.5
C
i
V
OH
V
OL
I
DD
I
DDD
I
O
= 0
pF
V
V
I
= V
DDQ
or GND
CONDITIONS
V
I
= V
REF
±350mV
V
ICR
= 1.25V, V
I(PP)
= 360mV
1.8V
1.9V
1.8V
V
I
= V
REF
± 250 mV
V
ICR
= 0.9V; V
I(PP)
= 600 mV
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
V
DD
= 1.8V ± 0.1V
MIN
1
1
MAX
4
4
1
dV/dt_r
dV/dt_f
dV/dt_
1
V/ns
V/ns
V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER
UNIT
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