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參數(shù)資料
| 型號： | ICSSSTUA32S869B |
| 英文描述： | 14-Bit Configurable Registered Buffer for DDR2 |
| 中文描述： | 14位可配置的注冊緩沖DDR2內(nèi)存 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ICSSSTUA32S869B |
13
ICSSSTUA32S869B
Advance Information
1173—10/28/05
Notes: 1. C
L
incluces probe and jig capacitance.
2. I
DD
tested with clock and data inputs held at V
DD
or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR
≤
10 MHz,
Zo=50
, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. V
REF
= V
DD
/2
6. V
IH
= V
REF
+ 250 mV (ac voltage levels) for differential inputs. V
IH
= V
DD
for LVCMOS input.
7. V
IL
= V
REF
- 250 mV (ac voltage levels) for differential inputs. V
IL
= GND for LVCMOS input.
8. V
ID
= 600 mV
9. t
PLH
and t
PHL
are the same as t
PDM
.
Figure 6 — Parameter Measurement Information (V
DD
= 1.8 V ± 0.1 V)
R
L
= 1000
C
L
= 30 pF
(see Note 1)
LOAD CIRCUIT
t
w
V
ICR
V
ICR
Input
V
IH
V
IL
VOLTAGE WAVEFORMS – PULSE DURATION
V
REF
V
REF
Input
t
su
t
h
V
ID
V
ICR
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
V
ICR
V
ID
V
ICR
Output
V
OL
V
OH
V
TT
V
TT
t
PHL
t
PLH
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
t
RPHL
V
OL
V
OH
V
IL
V
IH
Output
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
V
DD
/2
V
TT
t
act
t
inact
LVCMOS
Input
RST#
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
I
(see
Note 2)
9
0%
10%
0 V
V
DD
Test Point
V
DD
/2
V
DD
/2
LVCMOS
RESET#
Input
TL=350ps, 50
DUT
CK#
CK
Out
TL
td = 350ps
=50
CK Inputs
V
ID
CK
CK
CK
CK
R
L
= 100
Test Point
Test Point
R
L
= 1000
V
DD
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