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參數(shù)資料
| 型號(hào)： | ICSSSTUA32S869B |
| 英文描述： | 14-Bit Configurable Registered Buffer for DDR2 |
| 中文描述： | 14位可配置的注冊(cè)緩沖DDR2內(nèi)存 |
| 文件頁(yè)數(shù)： | 12/18頁(yè) |
| 文件大?。?/td> | 303K |
| 代理商： | ICSSSTUA32S869B |
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12
ICSSSTUA32S869B
Advance Information
1173—10/28/05
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
340
10
15
f
clock
t
ACT
t
INACT
t
S
Clock frequency
Differential inputs active time
Differential inputs inactive time
Setup time
MHz
ns
ns
Data before CLK
↑
, CLK#
↓
DCS0 before CLK
↑
, CLK#
↓
,
CSR# high
DCS#, DODT, DCKE and Q
after CK
↑
, CK#
↓
0.5
0.7
Hold time
0.30
ns
Hold time
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
PARIN1 after CK
↑
, CK#
↓
0.30
ns
4 - CLK/CLK# signal input slew rate of 1V/ns.
SYMBOL
Notes:
t
H
V
DD
= 1.8V ±0.1V
UNITS
PARAMETERS
ns
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement
Conditions
MIN
MAX
Units
fmax
Max input clock frequency
340
MHz
t
PDM
Propagation delay, single
bit switching
Low to High propagation
delay
High to low propagation
delay
Propagation delay
simultaneous switching
High to low propagation
delay
Low to High propagation
delay
1. Guaranteed by design, not 100% tested in production.
CK
↑
to CK#
↓
QN
1.2
1.9
ns
t
LH
CK
↑
to CK#
↓
to
PTYERR#
CK
↑
to CK#
↓
to
PTYERR#
1.2
3
ns
t
HL
1
3
ns
t
PDMSS
CK
↑
to CK#
↓
QN
2
ns
t
PHL
RESET#
↓
to QN
↓
3
ns
t
PLH
RESET#
↓
to
PTYERR1#
↑
3
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICSSSTUAF32865A | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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| ICSSSTUAF32866B | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32866BHLFT | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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