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參數(shù)資料
| 型號： | ICSSSTUA32S869B |
| 英文描述： | 14-Bit Configurable Registered Buffer for DDR2 |
| 中文描述： | 14位可配置的注冊緩沖DDR2內存 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ICSSSTUA32S869B |
3
ICSSSTUA32S869B
Advance Information
1173—10/28/05
Parity and Standby Function Table
RESET#
DCS#
CSR#
CK
CK#
￡ of inputs = H
D1..…14
(1)
PARIN1
(2)
PPO1
(2)
PTYERR1#
(3)
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
X
X
X
X
X
L
L
L
L
H
X
↑
↑
↑
↑
↑
↑
↑
↑
↑
↓
↓
↓
↓
↓
↓
↓
↓
↓
Even
Odd
Even
Odd
Even
Odd
Even
Odd
X
X
X or
floating
L
L
H
H
L
L
H
H
X
X
L
H
H
L
L
H
H
L
H
L
L
H
H
L
L
H
PPOn
0
PPOn
0
PTYERRn
0
#
PTYERRn
0
#
L or H
X or
floating
L or H
X or
floating
L
X or
floating
X or
floating
X or
floating
L
H
NOTE 1
NOTE 2
NOTE 3 This transition assumes PTYERR1# is high at the crossing of CK going high and CK# going low.
If PTYERR1# is low, it stays latched low for two clock cycles or until RESET# is driven low. PARIN1 is
used to generate PPO1 and PTYERR1#.
Inputs
Output
Inputs D1, D4 and D4 are not included in this range.
PARIN1 arrives one (C1 = 0) or two (C = 1) clock cycles after data to which it applies.
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相關代理商/技術參數(shù) |
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| ICSSSTUAF32865A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32865AHLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32866B | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32866BHLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32866C | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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