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參數(shù)資料
| 型號： | ICSSSTUA32S869B |
| 英文描述： | 14-Bit Configurable Registered Buffer for DDR2 |
| 中文描述： | 14位可配置的注冊緩沖DDR2內(nèi)存 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大小： | 303K |
| 代理商： | ICSSSTUA32S869B |
15
ICSSSTUA32S869B
Advance Information
1173—10/28/05
Error output load circuit and voltage measurement information (V
DD
= 1.8 V ± 0.1 V)
All input pulses are supplied by generators having the following characteristics: PRR
10 MHz;
Z
o
= 50
; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) C
L
includes probe and jig capacitance.
Figure 16 — Load circuit, error output measurements
Figure 17 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET#
input
Figure 18 — Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock
inputs
Figure 19 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock
inputs
CL = 10 pF
SEE NOTE (1)
VDD
OUT
DUT
TEST POINT
RL = 1 k
002aaa500
VCC/2
tPLH
VCC
0 V
0.15 V
VOH
0 V
Output
Waveform 2
LVCMOS
RESET
Input
002aaa501
VICR
tHL
VCC/2
VCC
VOL
Timing
Inputs
Output
Waveform 1
VI(PP)
VICR
002aaa502
VICR
tLH
VOH
0 V
Timing
Inputs
Output
Waveform 2
VI(PP)
VICR
0.15 V
002aaa503
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| ICSSSTUAF32866BHLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32866C | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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