參數(shù)資料
型號(hào)： ICSSSTUB32866B
英文描述： 25-Bit Configurable Registered Buffer for DDR2
中文描述： 25位可配置的注冊(cè)緩沖DDR2內(nèi)存
文件頁(yè)數(shù)： 22/28頁(yè)
文件大?。?/td> 554K
代理商： ICSSSTUB32866B
22
ICSSSTUB32866B
Advance Information
1165—10/25/06
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement
Conditions
MIN
MAX
Units
fmax
Max input clock frequency
410
MHz
t
PDM
Propagation delay, single
bit switching
Propagation delay
Low to High propagation
delay
High to low propagation
delay
Propagation delay
simultaneous switching
High to low propagation
delay
High to low propagation
delay
Low to High propagation
delay
2. Guaranteed by design, not 100% tested in production.
CK
↑
to CK#
↓
QN
1.1
1.9
ns
t
PD
CK
↑
to CK#
↓
to PPO
0.5
1.8
ns
t
LH
CK
↑
to CK#
↓
to QERR#
1.2
3
ns
t
HL
CK
↑
to CK#
↓
to QERR#
1
2.4
ns
t
PDMSS
CK
↑
to CK#
↓
QN
-
2
ns
t
PHL
Rst#
↓
to QN
↓
3
ns
t
PHL
Rst#
↓
to PPO
↓
3
ns
t
PLH
Rst#
↓
to QERR#
↑
3
ns
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
-
1
MAX
410
-
f
clock
t
W
t
ACT
t
INACT
Clock frequency
Pulse duration, CK, CK HIGH or LOW
MHz
ns
Differential inputs active time (See Notes 1 and 2)
-
10
ns
Differential inputs inactive time (See Notes 1 and 3)
-
15
ns
t
su
Setup time
DSR# before CK
↑
, CK#
↓
,
CSR# high
CSR# before CK
↑
, CK#
↓
,
DCS# high
DCS# before CK
↑
, CK#
↓
,
CSR# low
DODT, DCKE and data before
CK
↑
, CK#
↓
PAR_IN before CK
↑
, CK#
↓
0.6
ns
t
su
Setup time
0.6
ns
t
su
Setup time
0.5
ns
t
su
Setup time
0.5
ns
t
su
Setup time
0.5
ns
Hold time
DCS#, DODT, DCKE and Q
after CK
↑
, CK#
↓
0.40
ns
Hold time
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
PAR_IN after CK
↑
, CK#
↓
0.40
ns
4 - CLK/CLK# signal input slew rate of 1V/ns.
SYMBOL
Notes:
t
H
V
DD
= 1.8V ±0.1V
UNITS
PARAMETERS
相關(guān)PDF資料
PDF描述
ICSSSTUB32866Bz(LF)T 25-Bit Configurable Registered Buffer for DDR2
ICSSSTUB32871A 27-Bit Registered Buffer for DDR2
ICSSSTUB32871AzLFT 27-Bit Registered Buffer for DDR2
ICSSSTUB32871AzT 27-Bit Registered Buffer for DDR2
ICSSSTUB32872A 28-Bit Registered Buffer for DDR2
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICSSSTUB32866BZ(LF)T 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2
ICSSSTUB32871A 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2
ICSSSTUB32871AZLFT 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2
ICSSSTUB32871AZT 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2
ICSSSTUB32872A 制造商:ICS 制造商全稱:ICS 功能描述:28-Bit Registered Buffer for DDR2
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*