參數(shù)資料
型號(hào): ICSSSTUB32866B
英文描述: 25-Bit Configurable Registered Buffer for DDR2
中文描述: 25位可配置的注冊(cè)緩沖DDR2內(nèi)存
文件頁(yè)數(shù): 26/28頁(yè)
文件大?。?/td> 554K
代理商: ICSSSTUB32866B
26
ICSSSTUB32866B
Advance Information
1165—10/25/06
C
L
= 5pF
(1)
R
L
= 1K
Ω
DUT
Out
Test Point
V
TT
V
ICR
t
HL
V
I(PP)
Output
V
TT
CLK
CLK
V
ICR
t
HL
Partial parity out load circuit
Partial parity out voltage waveform, propagation
delay time with respect to CLK input
V
TT
= V
DD
/2
V
I(P-P)
= 600mV
t
PLH
and t
PHL
are the same as t
PD
V
TT
= V
DD
/2
t
PLH
and t
PHL
are the same as t
PD
V
IH
= V
REF
+ 250mV (AC voltage levels) for differential inputs. V
IH
= V
DD
for LVCMOS inputs.
V
IL
= V
REF
- 250mV (AC voltage levels) for differential inputs. V
IL
= V
DD
for LVCMOS inputs.
V
IH
Output
V
DD
/2
Input
LVCMOS RESET
V
IL
V
OH
V
OL
V
TT
t
PHL
Partial parity out voltage waveform, propagation
delay time with respect to RESET input
相關(guān)PDF資料
PDF描述
ICSSSTUB32866Bz(LF)T 25-Bit Configurable Registered Buffer for DDR2
ICSSSTUB32871A 27-Bit Registered Buffer for DDR2
ICSSSTUB32871AzLFT 27-Bit Registered Buffer for DDR2
ICSSSTUB32871AzT 27-Bit Registered Buffer for DDR2
ICSSSTUB32872A 28-Bit Registered Buffer for DDR2
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICSSSTUB32866BZ(LF)T 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2
ICSSSTUB32871A 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2
ICSSSTUB32871AZLFT 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2
ICSSSTUB32871AZT 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2
ICSSSTUB32872A 制造商:ICS 制造商全稱:ICS 功能描述:28-Bit Registered Buffer for DDR2