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參數(shù)資料
| 型號： | ICSSSTUB32866Bz(LF)T |
| 英文描述： | 25-Bit Configurable Registered Buffer for DDR2 |
| 中文描述： | 25位可配置的注冊緩沖DDR2內(nèi)存 |
| 文件頁數(shù)： | 23/28頁 |
| 文件大?。?/td> | 554K |
| 代理商： | ICSSSTUB32866BZ(LF)T |
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23
ICSSSTUB32866B
Advance Information
1165—10/25/06
Notes: 1. C
L
incluces probe and jig capacitance.
2. I
DD
tested with clock and data inputs held at V
DD
or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR
≤
10 MHz,
Zo=50
Ω
, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. V
REF
= V
DD
/2
6. V
IH
= V
REF
+ 250 mV (ac voltage levels) for differential inputs. V
IH
= V
DD
for LVCMOS input.
7. V
IL
= V
REF
- 250 mV (ac voltage levels) for differential inputs. V
IL
= GND for LVCMOS input.
8. V
ID
= 600 mV
9. t
PLH
and t
PHL
are the same as t
PDM
.
C
L
= 30 pF
R
L
= 1000
Ω
DUT
Out
R
L =
100
Ω
CK Inputs
T
L
= 50
Ω
T
L
= 350ps, 50
Ω
Test Point
V
DD
0V
V
DD
/2
LVCMOS
RST#
Input
I
DD
V
DD
/2
t
INACT
t
ACT
10%
90%
CK#
V
ICR
V
ID
t
PLH
t
PHL
Output
V
OH
V
OL
V
ICR
V
TT
V
TT
V
OH
V
OL
V
IH
V
IL
t
RPHL
V
DD
/2
V
TT
LVCMOS
RST#
Input
Output
V
ICR
V
ID
V
ICR
Input
t
W
V
REF
V
IH
V
IL
V
REF
Input
V
ICR
V
ID
t
SU
t
H
CK#
CK
V
DD
R
L
= 1000
Ω
Test Point
Test Point
CK
(1)
(2)
CK#
CK
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Figure 6
Parameter Measurement Information (V
DD
= 1.8V ± 0.1V)
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