參數(shù)資料
型號(hào): ICSSSTUB32866Bz(LF)T
英文描述: 25-Bit Configurable Registered Buffer for DDR2
中文描述: 25位可配置的注冊(cè)緩沖DDR2內(nèi)存
文件頁數(shù): 27/28頁
文件大?。?/td> 554K
代理商: ICSSSTUB32866BZ(LF)T
27
ICSSSTUB32866B
Advance Information
1165—10/25/06
Ordering Information
ICSSSTUB32866Bz(LF)T
Example:
ICS XXXX
y
z (LF) T
D
E
T
e
HORIZ
6
6
VERT
16
16
TOTAL
96
96
d
h
b
c
Min/Max
1.20/1.40
1.00/1.20
Min/Max
0.40/0.50
0.35/0.45
Min/Max
0.25/0.41
0.25/0.35
13.50 Bsc
11.50 Bsc
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
5.50 Bsc
5.00 Bsc
0.80 Bsc
0.65 Bsc
0.75
0.875
0.75
0.875
MO-205
10-0055C
* Source Ref.: JEDEC Publication 95,
ALL DIMENSIONS IN MILLIMETERS
REF. DIMENSIONS
----- BALL GRID ----- Max.
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
H = LFBGA (standard size: 5.5 x 13.50)
HM = TFBGA (reduced size: 5.0 x 11.50)
Revision Designator
(will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
SEATING
PLANE
0.12
C
C
A
B
C
D
A1
D
E
TOP VIEW
T
h TYP
d TYP
4
3
2
1
Numeric Designations
for Horizontal Grid
b REF
c REF
TYP
-e-
TYP
-e-
D1
E1
Alpha Designations
for Vertical Grid
(Letters I, O, Q, and
S not used)
相關(guān)PDF資料
PDF描述
ICSSSTUB32871A 27-Bit Registered Buffer for DDR2
ICSSSTUB32871AzLFT 27-Bit Registered Buffer for DDR2
ICSSSTUB32871AzT 27-Bit Registered Buffer for DDR2
ICSSSTUB32872A 28-Bit Registered Buffer for DDR2
ICSSSTUBF32866A 25-Bit Configurable Registered Buffer for DDR2
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICSSSTUB32871A 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2
ICSSSTUB32871AZLFT 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2
ICSSSTUB32871AZT 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2
ICSSSTUB32872A 制造商:ICS 制造商全稱:ICS 功能描述:28-Bit Registered Buffer for DDR2
ICSSSTUBF32866A 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2