參數(shù)資料
型號(hào)： IDT5T2110NLGI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68
封裝： GREEN, PLASTIC, VFQFP-68
文件頁(yè)數(shù)： 2/24頁(yè)
文件大?。?/td> 207K
代理商： IDT5T2110NLGI8
10
INDUSTRIALTEMPERATURERANGE
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR eHSTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(7)
Max
Unit
InputCharacteristics
IIH
Input HIGH Current
VDD = 2.7V
VI = VDDQ/GND
—
±5
A
IIL
InputLOWCurrent
VDD = 2.7V
VI = GND/VDDQ
——
±5
VIK
ClampDiodeVoltage
VDD = 2.3V, IIN = -18mA
—
- 0.7
- 1.2
V
VIN
DCInputVoltage
- 0.3
+3.6
V
VDIF
DCDifferentialVoltage(2,8)
0.2
—
V
VCM
DC Common Mode Input Voltage(3,8)
800
900
1000
mV
VIH
DC Input HIGH(4,5,8)
VREF + 100
—
mV
VIL
DC Input LOW(4,6,8)
—VREF - 100
mV
VREF
Single-EndedReferenceVoltage(4,8)
—
900
—
mV
OutputCharacteristics
VOH
Output HIGH Voltage
IOH = -8mA
VDDQ - 0.4
—
V
IOH = -100
AVDDQ - 0.1
—
V
VOL
OutputLOWVoltage
IOL = 8mA
—
0.4
V
IOL = 100
A
—
0.1
V
VOX
Qn/Qn and FB/FB Output Crossing Point
VDDQ/2 - 150
VDDQ/2
VDDQ/2 + 150
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in a differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
POWER SUPPLY CHARACTERISTICS FOR eHSTL OUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
15
25
mA
PLL_EN = HIGH, DS[1:0]
= MM, nF[2:1] = LH,
FBF[2:1] =LH,Outputsenabled,Alloutputsunloaded
IDDQQ
Quiescent VDDQ Power Supply Current(3)
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,
1.7
50
A
PLL_EN = HIGH, DS[1:0]
= MM, nF[2:1] = LH,
FBF[2:1] =LH,Outputsenabled,Alloutputsunloaded
IDDPD
Power Down Current
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
0.8
3
mA
IDDD
Dynamic VDD Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
13
20
A/MHz
CurrentperOutput
IDDDQ
Dynamic VDDQ Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
20
30
A/MHz
CurrentperOutput
ITOT
Total Power VDD Supply Current(4)
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF
35
55
mA
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF
55
85
ITOTQ
Total Power VDDQ Supply Current(4)
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF
50
75
mA
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF
115
175
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH
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