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參數(shù)資料
| 型號： | IDT5T2110NLGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68 |
| 封裝： | GREEN, PLASTIC, VFQFP-68 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 207K |
| 代理商： | IDT5T2110NLGI8 |
12
INDUSTRIALTEMPERATURERANGE
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL
Symbol
Parameter
Value
Units
VDIF
Input Signal Swing(1)
732
mV
VX
DifferentialInputSignalCrossingPoint(2)
1082
mV
VTHI
InputTimingMeasurementReferenceLevel(3)
CrossingPoint
V
tR, tF
InputSignalEdgeRate(4)
1
V/ns
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 2.5V
LVTTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(8)
Max
Unit
InputCharacteristics
IIH
Input HIGH Current
VDD = 2.7V
VI = VDDQ/GND
—
±5
A
IIL
InputLOWCurrent
VDD = 2.7V
VI = GND/VDDQ
——
±5
VIK
ClampDiodeVoltage
VDD = 2.3V, IIN = -18mA
—
- 0.7
- 1.2
V
VIN
DCInputVoltage
- 0.3
+3.6
V
Single-Ended Inputs(2)
VIH
DC Input HIGH
1.7
—
V
VIL
DC Input LOW
—
0.7
V
DifferentialInputs
VDIF
DCDifferentialVoltage(3,9)
0.2
—
V
VCM
DC Common Mode Input Voltage(4,9)
1150
1250
1350
mV
VIH
DC Input HIGH(5,6,9)
VREF + 100
—
mV
VIL
DC Input LOW(5,7,9)
—VREF - 100
mV
VREF
Single-EndedReferenceVoltage(5,9)
—
1250
—
mV
OutputCharacteristics
VOH
Output HIGH Voltage
IOH = -12mA
VDDQ - 0.4
—
V
IOH = -100
AVDDQ - 0.1
—
V
VOL
OutputLOWVoltage
IOL = 12mA
—
0.4
V
IOL = 100
A
—
0.1
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and REF[1:0]/VREF[1:0] is left floating. If TxS is HIGH, FB/VREF2 should be left floating.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
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