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參數(shù)資料
| 型號(hào)： | IDT5T2110NLGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68 |
| 封裝： | GREEN, PLASTIC, VFQFP-68 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 207K |
| 代理商： | IDT5T2110NLGI8 |
5
INDUSTRIALTEMPERATURERANGE
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
PIN DESCRIPTION, CONTINUED
Symbol
I/O
Type
Description
REF_SEL
I
LVTTL(1)
Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1.
nsOE
I
LVTTL(1)
Synchronousoutputenable. WhennsOE isHIGH,nQandnQ aresynchronouslystopped. OMODEselectswhethertheoutputsare
gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/HIGH,
the nQ is stopped in a HIGH/LOW state, while the nQ is stopped at a LOW/HIGH state. When OMODE is LOW, the outputs are tri-
stated. Set nsOE LOW for normal operation.
QFB
O
Adjustable(2)
Feedbackclockoutput
QFB
O
Adjustable(2)
Complementaryfeedbackclockoutput
nQ
O
Adjustable(2)
Clockoutputs
nQ
O
Adjustable(2)
Complementaryclockoutputs
RxS
I
3-Level(3)
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF clock input
TxS
I
3-Level(3)
Setsthedrivestrengthoftheoutputdriversandfeedbackinputstobe2.5VLVTTL(HIGH),1.8VLVTTL(MID)oreHSTL/HSTL(LOW)
compatible. Used in conjuction with VDDQ to set the interface levels.
PE
I
LVTTL(1)
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference
clock(hasinternalpull-up).
nF[2:1]
I
LVTTL(1)
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on each bank. (See Control Summary table.)
FBF[2:1]
I
LVTTL(1)
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on the feedback bank (See Control Summary table)
FS
I
LVTTL(1)
Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange(SeeVCOFrequencyRangeSelecttable)
DS[1:0]
I
3-Level(3)
3-levelinputsforfeedbackinputdividerselection(SeeDivideSelectiontable)
PLL_EN
I
LVTTL(1)
PLLenable/disablecontrol. SetLOWfornormaloperation. WhenPLL_ENisHIGH,thePLLisdisabledandREF[1:0]goestoalloutputs.
PD
I
LVTTL(1)
Powerdowncontrol. WhenPDisLOW,theinputsaredisabledandinternalswitchingisstopped. OMODEselectswhethertheoutputs
are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/
HIGH, the nQ and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a LOW/HIGH state. When OMODE
is LOW, the outputs are tri-stated. Set PD HIGH for normal operation.
LOCK
O
LVTTL
PLLlockindicationsignal. HIGHindicateslock. LOWindicatesthatthePLLisnotlockedandoutputsmaynotbesynchronized tothe
inputs. The output will be 2.5V LVTTL. (For more information on application specific use of the LOCK pin, please see AN237.)
OMODE
I
LVTTL(1)
Outputdisablecontrol. Determinestheoutputs'disablestate. UsedinconjunctionwithnsOEandPD. (SeeOutputEnable/Disableand
Powerdowntables.)
VDDQ
PWR
Power supply for output buffers. When using 2.5V LVTTL, VDDQshould be connected to VDD.
VDD
PWR
Powersupplyforphaselockedloop,lockoutput,inputs,andotherinternalcircuitry
GND
PWR
Ground
VCO FREQUENCY RANGE SELECT
FS(1)
Min.
Max.
Unit
LOW
50
125
MHz
HIGH
100
250
MHz
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ
is stopped in a HIGH/LOW state while the nQ is stopped at a LOW/HIGH state.
OUTPUTENABLE/DISABLE
nsOE
OMODE
Output
L
X
NormalOperation
H
L
Tri-State
H
Gated(1)
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ
and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a
LOW/HIGH state.
POWERDOWN
PD
OMODE
Output
H
X
NormalOperation
L
Tri-State
L
H
Gated(1)
NOTE:
1. The level to be set on FS is determined by the nominal operating frequency of the
VCO. The VCO frequency (FNOM) always appears at nQ and nQ outputs when they
are operated in their undivided modes. The frequency appearing at the REF[1:0] and
REF[1:0] /VREF[1:0] and FB and FB/VREF2 inputs will be FNOM when the QFB and QFB
are undivided and DS[1:0] = MM. The frequency of REF[1:0] and REF[1:0] /VREF[1:0]
and FB and FB/VREF2 inputs will be FNOM/2 or FNOM/4 when the part is configured for
frequency multiplication by using a divided QFB and QFB and setting DS[1:0] = MM.
Using the DS[1:0] inputs allows a different method for frequency multiplication (see
Divide Selection table).
NOTES:
1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V LVTTL signals as well.
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
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