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參數資料
| 型號： | IDT5T2110NLGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68 |
| 封裝： | GREEN, PLASTIC, VFQFP-68 |
| 文件頁數： | 6/24頁 |
| 文件大?。?/td> | 207K |
| 代理商： | IDT5T2110NLGI8 |
14
INDUSTRIALTEMPERATURERANGE
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 1.8V
LVTTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(8)
Max
Unit
InputCharacteristics
IIH
Input HIGH Current
VDD = 2.7V
VI = VDDQ/GND
—
±5
A
IIL
InputLOWCurrent
VDD = 2.7V
VI = GND/VDDQ
——
±5
VIK
ClampDiodeVoltage
VDD = 2.3V, IIN = -18mA
—
- 0.7
- 1.2
V
VIN
DCInputVoltage
- 0.3
VDDQ + 0.3
V
Single-Ended Inputs(2)
VIH
DC Input HIGH
1.073(10)
—V
VIL
DC Input LOW
—
0.683(11)
V
DifferentialInputs
VDIF
DCDifferentialVoltage(3,9)
0.2
—
V
VCM
DC Common Mode Input Voltage(4,9)
825
900
975
mV
VIH
DC Input HIGH(5,6,9)
VREF + 100
—
mV
VIL
DC Input LOW(5,7,9)
—VREF - 100
mV
VREF
Single-EndedReferenceVoltage(5,9)
—
900
—
mV
OutputCharacteristics
VOH
Output HIGH Voltage
IOH = -6mA
VDDQ - 0.4
—
V
IOH = -100
AVDDQ - 0.1
—
V
VOL
OutputLOWVoltage
IOL = 6mA
—
0.4
V
IOL = 100
A
—
0.1
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is MID and REF[1:0]/VREF[1:0] is left floating. If TxS is MID, FB/VREF2 should be left floating.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. The input is guaranteed to toggle within ±200mV of VREF[1:0] when VREF[1:0]
is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the REF[1:0] input. To guarantee switching in voltage range
specified in the JEDEC 1.8V LVTTL interface specification, VREF[1:0] must be maintained at 900mV with appropriate tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 * VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIH = 0.65 * [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 * VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIL = 0.35 * [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.
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