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參數(shù)資料
| 型號： | IDT5T9820NLI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 19/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DRIVER ZD PLL 68-VFQFPN |
| 產(chǎn)品變化通告： | Product Discontinuation 05/Jan/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | PLL 時(shí)鐘驅(qū)動器 |
| PLL： | 帶旁路 |
| 輸入： | eHSTL，HSTL，LVPECL，LVTTL |
| 輸出： | eHSTL，HSTL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:10 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 250MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-VFQFPN（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 5T9820NLI8 |
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INDUSTRIALTEMPERATURERANGE
IDT5T9820
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL CLOCK DRIVER
I2C SERIAL INTERFACE CONTROL
The I2C interface permits the configuration of the IDT5T9820. The
IDT5T9820isaread/writeslavedevicemeetingPhilipsI2Cbusspecifications.
The I2C bus is controlled by a master device that generates the serial clock
SCLK,controlsbusaccess,andgeneratestheSTARTandSTOPconditions
while the device works as a slave. Both master and slave can operate as a
transmitter and receiver but the master device determines which mode is
activated.
BUS CONDITIONS
Datatransferonthebuscanonlybeinitiatedwhenthebusisnotbusy. During
datatransfer,thedataline(SDA)mustremainstablewhenevertheclockline
(SCLK) is high. Changes in the data line while the clock line is high will be
interpreted by the device as a START or STOP condition. The following bus
conditions are defined by the I2C bus protocol and are illustrated in figure 1.
NOT BUSY
Boththedata(SDA)andclock(SCLK)linesremainhightoindicatethebus
is not busy.
STARTDATATRANSFER
AhightolowtransitionoftheSDAlinewhiletheSCLKinputishighindicates
aSTARTcondition. AllcommandstothedevicemustbeprecededbyaSTART
condition.
STOP DATA TRANSFER
A low to high transition of the SDA line while SCLK is held high indicates a
STOP condition. All commands to the device must be followed by a STOP
condition.
DATA VALID
The state of the SDA line represents valid data if the SDA line is stable for
thedurationofthehighperiodoftheSCLKlineafteraSTARTconditionoccurs.
The data on the SDA line must be changed only during the low period of the
SCLKsignal. Thereisoneclockpulseperdatabit. Eachdatatransferisinitiated
by a START condition and terminated with a STOP condition.
ACKNOWLEDGE
When addressed, the receiving device is required to generate an
Acknowledge after each byte is received. The master device must generate
anextraclockpulsetocoincidewiththeAcknowledgebit. Theacknowledging
device must pull the SDA line low during the high period of the master
acknowledge clockpulse. Setup and hold times mustbe taken intoaccount.
I2C BUS OPERATION
I2C ADDRESS
A7
A6
A5
A4
A3
A2
A1
11
0
1
X
Address A0 is the read/write bit and is set to ‘0’ for writes and ‘1’ for reads.
The ADDR0 and ADDR1 tri-level pins allow the last three bits of the 7-bit
address to be defined by the user.
ADDR1
ADDR0
A3
A2
A1
LOW
0
LOW
MID
0
1
LOW
HIGH
0
1
0
MID
LOW
0
1
MID
1
0
MID
HIGH
1
0
1
HIGH
LOW
1
0
HIGH
MID
1
HIGH
1
0
WRITE OPERATION
(see I2C Interface Definition for ProgWrite)
Toinitiateawriteoperation(ProgWrite),theread/writebitissetto‘0’. During
thewriteoperation,thefirsttwobytestransferredmustbetheDeviceAddress
followed by the Command Code. The internal programming registers of the
deviceignorethesefirsttwobytes. ThesubsequentbytesaretheDataBytes,
whichtotaltwelve. AlltwelveDataBytesmustbewrittenintothedeviceduring
the write operation in order for the internal programming registers to be
updated. IfaSTOPconditionisgeneratedbeforethe12thDataByte,theinternal
programming registers will remain unchanged to prevent an invalid PLL
configuration. AnAcknowledgebythedevicebetweeneachbytemustoccur
before the next byte is sent. After the transfer of the 12th Data Byte, an
Acknowledge signal will be sent to the bus master after which it will generate
a STOP condition. Once the STOP condition has occurred, the internal
programming registers of the device will be updated.
READOPERATION
(see I2C Interface Definition for ProgRead)
Toinitiateareadoperation(ProgRead),theread/writebitissetto‘1’. During
thereadoperation,therewillbeatotaloffourteendatabytesreturnedfollowing
anAcknowledgeofthedeviceaddress. ThefirsttwodatabytesaretheIDByte
andaReservedByte,inthatorder. Thesubsequentbytesarethesametwelve
Data Bytes that were written during the write operation. The read back can
be terminated at any time by issuing a STOP condition.
JTAG/ I2C SERIAL CONFIGURATIONS:
VCO FREQUENCY SELECT
Bit 60
Min.
Max.
0
50Mhz
125MHz
1
100MHz
250Mhz
TheIDT5T9820I2CinterfacesupportsStandard-Mode(100kHz)andFast-
Mode(400kHz)datatransferrates. Dataistransferredinbytesinsequential
orderfromthelowesttohighestbyte. AftergeneratingaSTARTcondition,the
bus master broadcasts a 7-bit slave address followed by a read/write bit.
I2C ID BYTE
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
00
0
1
0
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| IDT5T9821NLGI | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9821NLGI8 | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9821NLI | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9821NLI8 | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9890NLGI | 功能描述:IC CLK DRIVER 2.5V PLL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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