參數(shù)資料
型號： IDT5T9820NLI8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 26/36頁
文件大?。?/td> 0K
描述： IC CLK DRIVER ZD PLL 68-VFQFPN
產(chǎn)品變化通告： Product Discontinuation 05/Jan/2011
標(biāo)準(zhǔn)包裝： 2,500
類型： PLL 時鐘驅(qū)動器
PLL： 帶旁路
輸入： eHSTL，HSTL，LVPECL，LVTTL
輸出： eHSTL，HSTL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:10
差分 - 輸入:輸出： 是/無
頻率 - 最大： 250MHz
除法器/乘法器： 是/無
電源電壓： 2.3 V ~ 2.7 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 68-VFQFPN（10x10）
包裝： 帶卷 (TR)
其它名稱： 5T9820NLI8
32
INDUSTRIALTEMPERATURERANGE
IDT5T9820
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL CLOCK DRIVER
THE INSTRUCTION REGISTER
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is
latchedatthecompletionoftheshiftingprocesswhentheTAPcontrollerisat
Update- IR state.
The instruction register must contain 4 bit instruction register-based cells
whichcanholdinstructiondata.Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEE Std. 1149.1-1990).
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in serial
31 (MSB)
28 27
12 11
1 0(LSB)
Version(4bits)
Partnumber
ManufacturerID
1
0X0
(16-bit)
(11-bit)0X33
path. Whenthebypassregisterisselectedbyaninstruction,theshiftregister
stageissettoalogiczeroontherisingedgeofTCLKwhentheTAPcontroller
is in the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports.TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is
dropped in the 11-bit Manufacturer ID field.
For the IDT5T9820, the Part Number field is 0x3A6.
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
when the TAP controller is in the Shift-IR state. The instruction is decoded to
performthefollowing:
Selecttestdataregistersthatmayoperatewhiletheinstructioniscurrent.
The other test data registers should not interfere with chip operation and the
selecteddataregister.
IR (3)
IR (2)
IR (1)
IR (0)
Instruction
Function
0
EXTEST
Select boundary scan register
0
1
SAMPLE/PRELOAD
Select boundary scan register
0
1
0
IDCODE
Selectchipidentificationdataregister
0
1
Reserved
0
1
0
PROGWRITE
Writingtothevolatileprogrammingregisters
0
1
0
1
PROGREAD
Readingfromthevolatileprogrammingregisters
0
1
0
PROGSAVE
Saving the contents of the volatile programming registers to the EEPROM
0
1
PROGRESTORE
Loading the EEPROM contents into the volatile programming registers
1
0
CLAMP
JTAG
1
0
1
HIGHZ
JTAG
1
0
1
X
BYPASS
Select bypass register
1
X
BYPASS
Select bypass register
JTAG INSTRUCTION REGISTER DECODING
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4-bit field (i.e.IR3, IR2, IR1, IR0) to decode
sixteendifferentpossibleinstructions.Instructionsaredecodedasfollows.
JTAG DEVICE IDENTIFICATION
REGISTER
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