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參數(shù)資料
| 型號： | IDT5V49EE502NLGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 31/33頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 200MHZ 24VQFN |
| 特色產(chǎn)品： | VersaClock III Timing Devices |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 類型： | 時鐘發(fā)生器，多路復(fù)用器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（4x4） |
| 包裝： | 管件 |
| 其它名稱： | 800-1919 |
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IDT5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
7
IDT5V49EE502
REV N 092412
clocks are at different frequencies, the device will always
remain on the primary clock unless it is absent for two
secondary clock cycles. The secondary clock must always
run at a frequency less than or equal to the primary clock
frequency.
R
eference Divider, Feedback Divider, and
Output Divider
Each PLL incorporates a 7-bit reference divider (D[6:0]) and
a 12-bit feedback divider (N[11:0]) that allows the user to
generate four unique non-integer-related frequencies. Each
output divide supports 8-bit output-divider (PM and Q[7:0]).
The following equation governs how the output frequency is
calculated.
Where FIN is the reference frequency, M is the total
feedback-divider value, D is the reference divider value,
ODIV is the total output-divider value, and FOUT is the
resulting output frequency.
For PLL0,
M = 2 * N + A + 1 (for A>0)
M = 2 * N (for A = 0)
For PLL1, PLL2 and PLL3,
M = N
PM and Q[6:0] are the bits used to program the 8-bit
output-dividers for outputs OUT1-6. OUT0 does not have
any output divide along its path. The 8-bit output-dividers
will bypass or divide down the output banks' frequency with
even integer values ranging from 2 to 256.
There is the option to choose between disabling the
output-divider, utilizing a div/1, a div/2, or the 7-bit Q-divider
by using the PM bit. If the output is disabled, it will be driven
High, Low or High Impedance, depending on OEM[1:0].
Each bank, except for OUT0, has a PM bit. When disabled,
no clocks will appear at the output of the divider, but will
remain powered on. The output divides selection table is
shown below.
Note that the actual 7-bit Q-divider value has a 2 added to
the integer value Q and the outputs are routed through
another div/2 block. The output divider should never be
disabled unless the output bank will never be used during
normal operation. The output frequency range for LVTTL
outputs are from 4.9KHz to 200MHz. The output frequency
for LVPECL/LVDS/HCSL outputs range from 4.9KHz to
500MHz.
Spread Spectrum Generation (PLL0)
PLL0 supports spread spectrum generation capability,
which users have the option of turning on or off. Spread
spectrum profile, frequency, and spread amplitude are fully
programmable. The programmable spread spectrum
generation parameters are TSSC[3:0], NSSC[2:0],
SS_OFFSET[5:0], SD[3:0], DITH, and X2 bits. These bits
are in the memory address from 0xAC to 0xBD for PLL0.
The spread spectrum generation on PLL0 can be
enabled/disabled using the TSSC[3:0] bits. To enable
spread spectrum, set TSSC > '0' and set NSSC[2:0],
SS_OFFSET[5:0], SD[3:0], and the A[3:0] (in the total M
value) accordingly. To disable spread spectrum generation,
set TSSC = '0'.
TSSC[3:0]
These bits are used to determine the number of
phase/frequency detector cycles per spread spectrum cycle
(ssc) steps. The modulation frequency can be calculated
with the TSSC bits in conjunction with the NSSC bits. Valid
TSSC integer values for the modulation frequency range
from 5 to 14. Values of 0 - 4 and 15 should not be used.
NSSC[2:0]
These bits are used to determine the number of
delta-encoded samples used for a single quadrant of the
spread spectrum waveform. All four quadrants of the spread
spectrum waveform are mirror images of each other. The
modulation frequency is also calculated based on the NSSC
bits in conjunction with the TSSC bits. Valid NSSC integer
F
OUT =
M
D
(
)
F
IN *
ODIV
(Eq. 1)
Q[6:0]
PM
Output Divider
111 1111
0
Disabled
1/1
<111 1111
0
/2
1
/((Q[6:0] + 2) * 2)
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| IDT5V49EE502NLGI8 | 功能描述:IC PLL CLK GEN 200MHZ 24VQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V49EE503NLGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR 24QFN |
| IDT5V49EE503NLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 24QFN |
| IDT5V49EE504NLGI | 功能描述:IC PLL CLK GEN 200MHZ 24VQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| IDT5V49EE504NLGI8 | 功能描述:IC PLL CLK GEN 200MHZ 24VQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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