參數(shù)資料
型號(hào)： IDT5V49EE502NLGI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 33/33頁(yè)
文件大?。?/td> 0K
描述： IC PLL CLK GEN 200MHZ 24VQFN
特色產(chǎn)品： VersaClock III Timing Devices
標(biāo)準(zhǔn)包裝： 75
類(lèi)型： 時(shí)鐘發(fā)生器，多路復(fù)用器
PLL： 帶旁路
輸入： LVCMOS，LVTTL，晶體
輸出： HCSL，LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:5
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 500MHz
除法器/乘法器： 是/是
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 24-QFN（4x4）
包裝： 管件
其它名稱(chēng)： 800-1919
IDT5V49EE502
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
9
IDT5V49EE502
REV N 092412
Profile:
Waveform starts with SS_OFFSET, SS_OFFSET + SDJ,
SS_OFFSET + SDJ+1, etc.
Spread Spectrum Using Sinusoidal Profile
Example
FIN = 25MHz, FOUT = 100MHz, Fssc = 33KHz with center
spread of ±2%. Find the necessary spread spectrum
register settings.
Since the spread is center, the SS_OFFSET can be set to
'0'. Solve for the nominal M value; keep in mind that the
nominal M should be chosen to maximize
the VCO. Start with D = 1, using Eq.6 and Eq.7.
MNOM = 1200MHz / 25MHz = 48
Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we
have the nominal M value, we can determine TSSC and
NSSC by using Eq.8.
Nssc * Tssc = 25MHz / (33KHz * 4) = 190
However, using Eq. 2 and Eq.3, we find that the closest
value is when TSSC = 14 and NSSC = 6. Keep in mind to
maximize the number of samples used
to enhance the profile of the spread spectrum waveform.
Tssc = 14 + 2 = 16
Nssc = 6 * 2 = 12
Nssc * Tssc = 192
Use Eq.10 to determine the value of the
sigma-delta-encoded samples.
±2% =
(ΣΔ * 100)/(64 * 48)
ΣΔ = 61.4
Either round up or down to the nearest integer value.
Therefore, we end up with 61 or 62 for sigma-delta-encoded
samples. Since the sigma-delta-encoded samples must not
exceed 63 with SS_OFFSET set to '0', 61 or 62 is well within
the limits. It is the discretion of the user to define the shape
of the profile that is better suited for the intended application.
Using Eq. 9 again, the actual spread for the
sigma-delta-encoded samples of 56 and 57 are ±1.99% and
±2.02%, respectively.
Use Eq.10 to determine if the X2 bit needs to be set;
Amplitude = 48 * (1.99 or 2.02) / 100/2 = 0.48 < 1
Therefore, the X2 = '0 '. The dither bit is left to the discretion
of the user.
The example above was of a center spread using spread
spectrum. For down spread, the nominal M value can be set
one integer value lower to 47.
Note that the IDT5V49EE502 should not be programmed
with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to
prevent an unstable state in the modulator.
The PLL loop bandwidth must be at least 10x the
modulation frequency along with higher damping (larger
ωuz) to prevent the spread spectrum from being filtered and
reduce extraneous noise. Refer to the LOOP FILTER
section for more detail on
ωuz. The A[3:0] must be used for
spread spectrum, even if the total multiplier value is an even
integer.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT5V49EE502NLGI8 功能描述:IC PLL CLK GEN 200MHZ 24VQFN RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱(chēng):844S012AKI-01LFT
IDT5V49EE503NLGI 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR 24QFN
IDT5V49EE503NLGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 24QFN
IDT5V49EE504NLGI 功能描述:IC PLL CLK GEN 200MHZ 24VQFN RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):NJW1504V-TE1-NDNJW1504V-TE1TR
IDT5V49EE504NLGI8 功能描述:IC PLL CLK GEN 200MHZ 24VQFN RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
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