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參數(shù)資料
| 型號： | IDT7140 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | High Speed 1K X 8 Dual-Port Static RAM(高速1K×8雙端口靜態(tài)RAM) |
| 中文描述： | 高速每1000 × 8雙端口靜態(tài)存儲器（高速每1000 × 8雙端口靜態(tài)RAM）的 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 214K |
| 代理商： | IDT7140 |
IDT7130SA/LA AND IDT7140SA/LA
HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
6.01
16
TRUTH TABLES
TRUTH TABLE II — INTERRUPT FLAG
(1,4)
o
P
t
L
TRUTH TABLE I — NON-CONTENTION READ/WRITE CONTROL
(4)
TRUTH TABLE III — ADDRESS BUSY
ARBITRATION
s
u
p
n
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs for IDT7130 (master). Both are
inputs for IDT7140 (slave).
BUSY
X
outputs on the IDT7130 are open drain,
not push-pull outputs. On slaves the
BUSY
X
input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If t
APS
is not met,
either
BUSY
L
or
BUSY
R
= LOW will result.
BUSY
L
and
BUSY
R
outputs can
not be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are
driving LOW regardless of actual logic level on the pin. Writes to the right
port are internally ignored when
BUSY
R
outputs are driving LOW regard-
less of actual logic level on the pin.
NOTES:
1. A
0L
– A
10L
≠
A
0R
– A
10R
.
2. If
BUSY
= L, data is not written.
3. If
BUSY
= L, data may not be valid, see t
WDD
and t
DDD
timing.
4. 'H' = V
IH
, 'L' = V
IL
, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
NOTES
:
1. Assumes
BUSY
L
=
BUSY
R
= V
IH
2. If
BUSY
L
= V
IL
, then No Change.
3. If
BUSY
R
= V
IL
, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
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