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參數(shù)資料
| 型號(hào)： | IDT71P73204 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 18Mb Pipelined DDR⑩II SRAM Burst of 4 |
| 中文描述： | 35.7流水線的DDR II SRAM的突發(fā)⑩4 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 648K |
| 代理商： | IDT71P73204 |
6.42
15
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range
AC Electrical Characteristics
(V
DD
= 1.8 ± 100mV, V
DDQ
= 1.4V to 1.9V, T
A
=0 to 70°C )
(3,7)
Symbol
Parameter
250MHz
200MHz
167MHz
Unit
Note
Mn.
Max
Mn.
Max
Mn.
Max
Clock Parameters
tKHKH
Average clock cycle time (K,
K
,C,
C
)
4.00
6.30
5.00
7.88
6.00
8.40
ns
tKC var
Cycle to Cycle Period Jitter (K,
K
,C,
C
)
-
0.20
-
0.20
-
0.20
ns
1,5
tKHKL
Clock High Time (K,
K
,C,
C
)
1.60
-
2.00
-
2.40
-
ns
8
tKLKH
Clock LOW Time (K,
K
,C,
C
)
1.60
-
2.00
-
2.40
-
ns
8
tKH
K
H
Clock to
clock
(K
→
K
, C
→
C
)
1.80
-
2.20
-
2.70
-
ns
9
t
K
HKH
Clock to
clock
(
K
→
K,
C
→
C)
1.80
-
2.20
-
2.70
-
ns
9
tKHCH
Clock to data clock (K
→
C,
K
→
C
)
0.00
1.80
0.00
2.30
0.00
2.80
ns
tKC lock
DLL lock time (K,C)
1024
-
1024
-
1024
-
cycles
2
tKC reset
K static to DLL reset
30
-
30
-
30
-
ns
Output Parameters
tCHQV
C,
C
HIGH to output valid
-
0.45
-
0.45
-
0.50
ns
3
tCHQX
C,
C
HIGH to output hold
-0.45
-
-0.45
-
-0.50
-
ns
3
tCHCQV
C,
C
HIGH to echo clock valid
-
0.45
-
0.45
-
0.50
ns
3
TCHCQX
C,
C
HIGH to echo clock hold
-0.45
-
-0.45
-
-0.50
-
ns
3
TCQHQV
CQ,
CQ
HIGH to output valid
-
0.30
-
0.35
-
0.40
ns
TCQHQX
CQ,
CQ
HIGH to output hold
-0.30
-
-0.35
-
-0.40
-
ns
TCHQZ
C HIGH to output HIGH-Z
-
0.45
-
0.45
-
0.50
ns
3,4,5
TCHQX1
C HIGH to output LOW-Z
-0.45
-
-0.45
-
-0.50
-
ns
3,4,5
Set-Up Time
tAVKH
Address valid to K,
K
rising edge
0.50
-
0.6
-
0.7
-
ns
6
tIVKH
R
,
W
inputs valid to K,
K
rising edge
0.50
-
0.6
-
0.7
-
ns
tDVKH
Data-in and
BWx
/
NWx
valid to K,
K
rising edge
0.35
-
0.40
-
0.50
-
ns
Hold Times
tKHAX
K,
K
rising edge to address hold
0.50
-
0.6
-
0.7
-
ns
6
tKHIX
K,
K
rising edge to
R
,
W
inputs hold
0.50
-
0.6
-
0.7
-
ns
tKHDX
K,
K
rising edge to data-in and
BWx
/
NWx
hold
0.35
-
0.40
-
0.50
-
ns
6431 tbl 11
NOTES:
1. Cycle to cycle period jitter is the variance fromclock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No.65
(EIA/JESD65) pg.10
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,
C
are tied High, K,
K
become the references for C,
C
timng parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0°C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70°C, 1.7V). It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals TA.
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to
clock
time (tKH
K
H) and
Clock
to clock time (t
K
HKH) should be within 45% to 55% of the cycle time (tKHKH).
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| IDT71P73604S167BQ | 功能描述:IC SRAM 18MBIT 167MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
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| IDT71P73604S200BQ | 功能描述:IC SRAM 18MBIT 200MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
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