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參數(shù)資料
| 型號(hào)： | IDT71P73204 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 18Mb Pipelined DDR⑩II SRAM Burst of 4 |
| 中文描述： | 35.7流水線的DDR II SRAM的突發(fā)⑩4 |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 648K |
| 代理商： | IDT71P73204 |
6.42
3
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range
Pin Definitions
Symbol
Pin Function
Description
DQ[X:0]
Input/Output
Synchronous
Data I/O signals. Data inputs are sampled on the rising edge of K and
K
during valid write operations. Data outputs are driven
during a valid read operation. The outputs are aligned wth the rising edge of both C and
C
during normal operation. When
operating in a single clock mode (C and
C
tied high), the outputs are aligned with the rising edge of both K and
K
. When a
Read operation is not initiated or
LD
is high (deselected) during the rising edge of K, DQ[X:O] are automatically driven to high
impedance after any previous read operation in progress completes.
2M x 8 -- DQ[7:0]
2M x 9 -- DQ[8:0]
1Mx 18 -- DQ[17:0]
512K x 36 -- DQ[35:0]
BW
0
,
BW
1
BW
2
,
BW
3
Input
Synchronous
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of
K
clocks
during write operations. Used to select which byte is written into the device during the current portion of the write operations.
Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written in to the device.
2M x 9 --
BW
0
controls DQ[8:0]
1Mx 18 --
BW
0
controls DQ[8:0] and
BW
1
controls DQ[17:9]
512K x 36 --
BW
0
controls DQ[8:0],
BW
1
controls DQ[17:9],
BW
2
controls DQ[26:18] and
BW
3
controls DQ[35:27]
NW
0,
NW
1
Input
Synchronous
Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the rising
edge of the K and
K
clocks during write operations. Used to select which nibble is written into the device during the current
portion of the write operations. Nibbles not written remain unaltered. All the nibble writes are sampled on the same edge as the
data. Deselecting a Nibble Write Select wll cause the corresponding nibble of data to be ignored and not written in to the
device.
2M x 8 --
NW0
controls D[3:0] and
NW1
controls D[7:4].
SA
Input
Synchronous
Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.
SA
0
, SA
1
Input
Synchronous
Burst count address bits on x18 and x36 DDRll devices. These bits allowchanging the burst order in read or write operations, or
addressing to the individual word of a burst. See page 9 for all possible burst sequences.
LD
Input
Synchronous
Load Control Logic. Sampled on the rising edge of K. If
LD
is low a four word burst read or write operation wll initiate
designated by the R/
W
input. If
LD
is high during the rising edge of K, operations in progress wll complete, but newoperations
wll not be initiated.
R/
W
Input
Synchronous
Read or Write Control Logic. If
LD
is lowduring the rising edge of K, the R/
W
indicates whether a newoperation should be a
read or write. If R/
W
is high, a read operation will be initiated, if R/
W
is low a write operation wll be initiated. If the
LD
input is
high during the rising edge of K, the R/
W
input wll be ignored.
C
Input Clock
Positive Output Clock Input. C is used in conjunction wth
C
to clock out the Read data fromthe device. C and
C
can be used
together to deskewthe flight times of various devices on the board back to the controller See application example for further
details.
C
Input Clock
Negative Output Clock Input.
C
is used in conjunction wth C to clock out the Read data fromthe device. C and
C
can be used
together to deskewthe flight times of various devices on the board back to the controller See application example for further
details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data
through DQ[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
K
Input Clock
Negative Input Clock Input.
K
is used to capture synchronous inputs being presented to the device and to drive out data through
DQ[X:0] when in single clock mode.
CQ,
CQ
Output Clock
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can
be used as a data valid indication. These signals are free running and do not stop when the output data is three stated.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the systemdata bus impedance. DQ[X:0]
output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
DDQ
, which enables the mnimumimpedance mode. This pin cannot be connected directly to GND or left
unconnected.
6431 tbl 02a
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| IDT71P73604S167BQ | 功能描述:IC SRAM 18MBIT 167MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| IDT71P73604S167BQ8 | 功能描述:IC SRAM 18MBIT 167MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| IDT71P73604S200BQ | 功能描述:IC SRAM 18MBIT 200MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| IDT71P73604S200BQ8 | 功能描述:IC SRAM 18MBIT 200MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| IDT71P73604S250BQ | 功能描述:IC SRAM 18MBIT 250MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
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