參數(shù)資料
型號(hào): IDT723616L20PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/26頁
文件大?。?/td> 0K
描述: IC FIFO TRPL BUS 64X36X2 128QFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 7200
功能: 同步
存儲(chǔ)容量: 4.6K(64 x 36 x2)
數(shù)據(jù)速率: 50MHz
訪問時(shí)間: 20ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 723616L20PF8
2
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
TQFP (PK128-1, ORDER CODE: PF)
TOP VIEW
PIN CONFIGURATION
Vcc
NC
3520 drw02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A26
A25
A24
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
A8
A7
Vcc
A6
A5
A4
A3
GND
A2
A1
A0
EFA
AEA
AFA
FFA
CSA
ENA
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
102
101
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
B8
B7
B6
B5
B4
B3
GND
B2
B1
B0
C17
C16
C15
C14
C13
C12
C11
C10
GND
C9
C8
C7
Vcc
C6
C5
C4
C3
GND
C1
C0
EFB
AEB
AFC
FFC
RENB
WENC
GND
A28
A27
GND
Vcc
A30
A31
A32
A33
A34
A35
GND
B17
B16
B15
B14
B13
B12
GND
Vcc
B10
B9
Vcc
GND
CLKA
W/
R
A
NC
V
c
P
G
A
PEFA
NC
SWC1
F
S
1
FS0
ODD/
EVEN
RST
GND
NC
SWC0
SWB1
SWB0
SIZ1
SIZ0
N
C
PEFC
P
G
B
Vcc
NC
CLKC
CLKB
104
103
INDEX
C2
A29
B11
number of words is stored in memory. Data on Port B can be accessed in 18-
bitand9-bitformats.FIFODataonPortCcanbeinputin18-bitand9-bitformats.
Byte-order swapping on ports B and C is possible with any bus size selection.
Parity is checked passively on ports A and C and may be ignored if not desired.
Parity generation can be selected for data read from ports A and B. Two or
more devices can be used in parallel to create wider or deeper FIFO
configurations.
This device is a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the LOW-
to-HIGH transition of a continuous (free-running) port clock by enable signals.
The clocks for each port are independent of one another and can be
asynchronous or coincident. The enables for each port are arranged to
provide a simple bidirectional interface between microprocessors and/or
buses controlled by a synchronous interface.
DESCRIPTION (CONTINUED)
NOTE:
1. NC - No internal connection.
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