參數(shù)資料
型號(hào): IDT723616L20PF8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 17/26頁(yè)
文件大?。?/td> 0K
描述: IC FIFO TRPL BUS 64X36X2 128QFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 7200
功能: 同步
存儲(chǔ)容量: 4.6K(64 x 36 x2)
數(shù)據(jù)速率: 50MHz
訪問(wèn)時(shí)間: 20ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 723616L20PF8
24
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
AFA
CLKA
RENB
3520 drw18
ENA
CLKB
1
2
tSKEW2
tENS
tENH
tPAF
tENS
tENH
tPAF
[64-(X+1)] Long Words in FIFO1
(64-X) Long Words in FIFO1
(1)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for
AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA
edge and rising CLKB edge is less than tSKEW2, then
AFA may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (
CSA = LOW, W/RA = HIGH).
3. Port-B size is word or byte; tSKEW2 is referenced from the last word or byte read of the long word, respectively.
Figure 18. Timing for
AFA
AFA when FIFO1 is Almost-Full
Figure 20. ODD/EVEN, W/
R
RR
RRA and PGA to PEFA
PEFA
PEFA Timing
AFC
CLKC
ENA
3520drw19
WENC
CLKA
12
tSKEW2
tENS
tENH
tPAF
tENS
tENH
tPAF
[64-(X+1)] Long Words in FIFO2
(64-X) Long Words in FIFO2
(1)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for
AFC to transition HIGH in the next CLKC cycle. If the time between the rising
CLKC edge and rising CLKA edge is less than tSKEW2, then
AFC may transition HIGH one CLKA cycle later than shown.
2. Port-C size is word or byte;
AFC is set LOW by the last word or byte read of the long word, respectively.
Figure 19. Timing for
AFC
AFC when FIFO2 is Almost-Full
3520 drw20
ODD/
EVEN
PEFA
PGA
W/RA
Valid
tPOPE
tPEPE
tPOPE
tPEPE
3520 drw21
ODD/
EVEN
PEFC
Valid
tPOPE
Figure 21. ODD/
EVEN
EVEN to PEFC
PEFC
PEFC Timing
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