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參數(shù)資料
| 型號： | IDT723616L20PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 22/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO TRPL BUS 64X36X2 128QFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 4.6K（64 x 36 x2） |
| 數(shù)據(jù)速率： | 50MHz |
| 訪問時間： | 20ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723616L20PF8 |
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5
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
Symbol
Name
I/O
Description
PEFC
Port C Parity Error
O
When any valid byte applied to terminals B0-B17 fails parity,
PEFC is LOW. Bytes are organized
Flag
as B0-B8 and B9-B17 with the most significant bit of each byte serving as the parity bit. A byte
is valid when it is used by the bus size selected for Port C. The type of parity checked is
determined by the state of the ODD/
EVEN input.
The parity trees used to check the B0-B17 inputs are shared by the mail 1 register to generate parity if
parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by
having WENC LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the
PEFC flag is forced HIGH
regardless of the state of the B0-B17 inputs.
PGA
Port A Parity
I
Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated
Generation
is selected by the state of the ODD/
EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26,
and A27-A35. The generated parity bits are output in the most significant bit of each byte.
PGB
Port B Parity
I
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated
Generation
is selected by the state of the ODD/
EVEN input. Bytes are organized as B0-B8 and B9-B17. The
generated parity bits are output in the most significant bit of each byte.
RENB
Port B Read Enable
I
RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on port B.
RST
Reset
I
To reset the device, four LOW-to-HIGH transitions of CLKA, four LOW-to-HIGH transitions of CLKB,
and four LOW-to-HIGH transitions of CLKC must occur while
RST is LOW. This sets the AFA and
AFC flags HIGH and the EFA, EFB, AEA, AEB, FFA, and FFC flags LOW. The LOW-to-HIGH
transition of
RST latches the status of the FS1 and FS0 inputs to select Almost-Full and Almost-
Emptyflagoffsets.
SIZ0, SIZ1
Bus Size Select
I
The levels on these inputs determine the bus size for ports B and C . These levels must be
(Ports B and C)
stable before Master Reset and must remain static for the duration of FIFO operation. Either
a word or a byte size may be selected for both ports B and C together; the ports cannot be
configured independently.
SWB0
Port B Byte Swap
I
The levels on these inputs select one of four modes of byte-order swapping for Port B. These levels
SWB1
must be stable before Master Reset and must remain static for the duration of FIFO operation. The
four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is
possible with any bus size selection.
SWC0
Port C Byte Swap
I
The levels on these inputs select one of four modes of byte-order swapping for Port C. These levels
must be stable before Master Reset and must remain static for the duration of FIFO operation. The
four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is
possible with any bus size selection.
W/
RA
Port A Write/Read
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
Select
transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/
RA is HIGH.
WENC
Port C Write Enable
I
A HIGH selects a Port C write operation for a LOW-to-HIGH transition of CLKC.
PIN DESCRIPTION (CONTINUED)
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| IDT723616L20PFI | 功能描述:IC FIFO TRPL BUS 64X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723616L20PFI8 | 功能描述:IC FIFO TRPL BUS 64X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723622L12PF | 功能描述:IC FIFO SYNC 256X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723622L12PF8 | 功能描述:IC FIFO SYNC 256X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723622L12PQF | 功能描述:IC FIFO SYNC 256X36X2 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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