參數(shù)資料
型號: IDT723616L20PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 24/26頁
文件大?。?/td> 0K
描述: IC FIFO TRPL BUS 64X36X2 128QFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 7200
功能: 同步
存儲容量: 4.6K(64 x 36 x2)
數(shù)據(jù)速率: 50MHz
訪問時間: 20ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 723616L20PF8
7
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
0
10
20
3040
5060
70
0
50
100
150
200
250
300
350
400
Clock Frequency MHz
fs
ICC(f)
Supply
Current
mA
f data = 1/2 f s
TA = 25
° C
C L = 0 pF
3520 drw04
80
VCC = 5.5V
VCC = 5V
VCC = 4.5V
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723616 with CLKA and CLKB set to
fs. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize
the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation
below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723616 can be calculated by:
PT = VCC x ICC(f) +
Σ(CL x VOH2 x fo)
where:
CL
=
output capacitance load
fo
=
switching frequency of an output
VOH
=
output high level voltage
When no reads or writes are occurring on the IDT723616, the power dissipated by a single clock (CLKA or CLKB) input running at frequency
fS is calculated by:
PT=VCC x fS x 0.290 mA/MHz
Figure 1. Typical Characteristics: Supply Current vs Clock Frequency
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