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參數(shù)資料
| 型號： | IDT723624L15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 256X36X2 128QFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 18.4K（256 x 36 x 2） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723624L15PF8 |
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10
COMMERCIALTEMPERATURERANGE
IDT723624/723634/723644 CMOS SyncBiFIFO WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SIGNAL DESCRIPTION
MASTER RESET (
MRS1, MRS2)
After power up, a Master Reset operation must be performed by providing
a LOW pulse to
MRS1andMRS2simultaneously. Afterwards,eachofthetwo
FIFO memories of the IDT723624/723634/723644 undergoes a complete
reset by taking its associated Master Reset (
MRS1, MRS2) input LOW for at
least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH
transitions. The Master Reset inputs can switch asynchronously to the clocks.
A Master Reset initializes the associated read and write pointers to the first
location of the memory and forces the Full/Input Ready flag (
FFA/IRA, FFB/
IRB) LOW, the Empty/Output Ready flag (
EFA/ORA, EFB/ORB) LOW, the
Almost-Empty flag (
AEA, AEB) LOW, and forces the Almost-Full flag (AFA,
AFB) HIGH. A Master Reset also forces the Mailbox Flag (MBF1, MBF2) of
the parallel mailbox register HIGH. After a Master Reset, the FIFO’s Full/Input
Ready flag is set HIGH after two write clock cycles. Then the FIFO is ready
to be written to.
A LOW-to-HIGH transition on a FlFO1 Master Reset (
MRS1)inputlatches
the value of the Big-Endian (BE) input for determining the order by which bytes
aretransferredthroughPortB.Italsolatchesthevaluesof theFlagSelect(FS0,
FS1) and Serial Programming Mode (
SPM) inputs for choosing the Almost-
Full and Almost-Empty offset programming method.
A LOW-to-HIGH transition on a FlFO2 Master Reset (
MRS2) clears the
FlagOffsetregistersofFIFO2(X2,Y2).ALOW-to-HIGHtransitionoftheFIFO2
Master Reset (
MRS2) together with the FIFO1 Master Reset (MRS1) input
latches the value of the Big-Endian (BE) input for the Port B and also latches
thevaluesof theFlagSelect(FS0,FS1)andSerialProgrammingMode(
SPM)
inputs for choosing the Almost-Full and Almost-Empty offset programming
method (for details see Table 1, Flag Programming, and the Programming
of the Almost-Empty and Almost-Full flagssection). The relevant FIFO Master
Reset timing diagram can be found in Figure 3.
PARTIAL RESET (
PRS1, PRS2)
Each of the two FIFO memories of these devices undergoes a limited reset
bytakingitsassociatedPartialReset(
PRS1,PRS2)inputLOWforatleastfour
Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions.
The Partial Reset inputs can switch asynchronously to the clocks. A Partial
Reset initializes the internal read and write pointers and forces the Full/Input
Ready flag (
FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/
ORA,
EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the
Almost-Fullflag(
AFA,AFB)HIGH.APartialResetalsoforcestheMailboxFlag
(
MBF1,MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,the
FIFO’s Full/Input Ready flag is set HIGH after two write clock cycles. Then the
FIFO is ready to be written to.
Whatever flag offsets, programming method (parallel or serial), and timing
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Reset is initiated, those settings will be remain unchanged upon completion of
the reset operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be inconvenient. See
Figure 4 for the Partial Reset timing diagram.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/
FWFT)
— ENDIAN SELECTION
Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction
is active, permitting a choice of Big or Little-Endian byte arrangement for data
written to or read from Port B. This selection determines the order by which
bytes (or words) of data are transferred through this port. For the following
illustrations, assume that a byte (or word) bus size has been selected for Port
B. (Note that when Port B is configured for a long word size, the Big-Endian
function has no application and the BE input is a “don’t care”1.)
A HIGH on the BE/
FWFT input when the Master Reset (MRS1 , MRS2)
inputs go from LOW to HIGH will select a Big-Endian arrangement. When data
is moving in the direction from Port A to Port B, the most significant byte (word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port B to Port A, the byte (word) written to
PortBfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong
word; the byte (word) written to Port B last will be read from Port A as the least
significant byte (word) of the long word.
A LOW on the BE/
FWFT input when the Master Reset (MRS1, MRS2)
inputsgofromLOWtoHIGHwillselectaLittle-Endianarrangement.Whendata
is moving in the direction from Port A to Port B, the least significant byte (word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port B to Port A, the byte (word) written to
PortBfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong
word; the byte (word) written to Port B last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figure 2 for an illustration of
the BE function. See Figure 3 (Master Reset) for the Endian select timing
diagram.
— TIMING MODE SELECTION
After Master Reset, the FWFT select function is active, permitting a choice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Master Reset (
MRS1,MRS2)inputisHIGH,
aHIGHontheBE/
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA
(for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode
uses the Empty Flag function (
EFA, EFB) to indicate whether or not there are
any words present in the FIFO memory. It uses the Full Flag function (
FFA,
FFB)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
In IDT Standard mode, every word read from the FIFO, including the first, must
be requested using a formal read operation. Refer to Figure 3 (Master Reset)
for a First Word Fall Through select timing diagram.
Once the Master Reset (
MRS1, MRS2) input is HIGH, a LOW on the BE/
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and
CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB)
to indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed by
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with
unused inputs) must not be left open, rather they must be either HIGH or LOW.
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| IDT723624L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 128TQFP |
| IDT723624L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 128TQFP |
| IDT723626L12PF | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L12PF8 | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L15PF | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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