參數(shù)資料
型號： IDT723624L15PF8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 31/35頁
文件大?。?/td> 0K
描述： IC FIFO SYNC 256X36X2 128QFP
標準包裝： 1,000
系列： 7200
功能： 同步
存儲容量： 18.4K（256 x 36 x 2）
數(shù)據(jù)速率： 67MHz
訪問時間： 15ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 帶卷 (TR)
其它名稱： 723624L15PF8
5
COMMERCIALTEMPERATURERANGE
IDT723624/723634/723644 CMOS SyncBiFIFO WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Symbol
Name
I/O
Description
FS1/
SEN FlagOffset
I
FS1/
SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Reset,
Select 1/
FS1/
SENandFS0/SD,togetherwith SPM,selecttheflagoffsetprogrammingmethod.Threeoffsetregister
Serial Enable,
programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load
from Port A, and serial load.
FS0/SD
FlagOffset
I
Select 0/
When serial load is selected for flag offset register programming, FS1/
SEN is used as an enable synchronous to
Serial Data
the LOW-to-HIGH transition of CLKA. When FS1/
SEN is LOW, a rising edge on CLKA load the bit present on
FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 32 for the
723624, 36 for the 723634, and 40 for the 723644. The first bit write stores the Y1 register MSB and the last bit
write stores the X2 register LSB.
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
Select
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects
FIFO2 output register data for output.
MBB
Port B Mailbox
I
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
Select
outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects
FIFO1 output register data for output.
MBF1
Mail1 Register
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the
Flag
mail1 register are inhibited while
MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when
a Port B read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset of
FIFO1.
MBF2
Mail2 Register
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the
Flag
mail2 register are inhibited while
MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a
Port A read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset of
FIFO2.
MRS1
FIFO1 Master
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
Reset
output register to all zeroes. A LOW-to-HIGH transition on
MRS1selectstheprogrammingmethod(serialorparallel)
and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures Port B for bus size and
endianarrangement. FourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
while
MRS1 is LOW.
MRS2
FIFO2 Master
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
Reset
output register to all zeroes. A LOW-to-HIGH transition on
MRS2toggledsimultaneouslywithMRS1,selectsthe
programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-
to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while
MRS2 is LOW.
PRS1
FIFO1 Partial
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
Reset
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, program
ming method (serial or parallel), and programmable flag settings are all retained.
PRS2
FIFO2 Partial
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
Reset
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, program
ming method (serial or parallel), and programmable flag settings are all retained.
SIZE(1)
Bus Size Select
I
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is
HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement
for Port B. The level of SIZE must be static throughout device operation.
SPM(1)
Serial Program-
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel
ming Mode
programming or default offsets (8, 16, or 64).
W/
RA
Port-AWrite/
I
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to- HIGH transition of
Read Select
CLKA. The A0-A35 outputs are in the HIGH impedance state when W/
RA is HIGH.
W/RB
Port-BWrite/
I
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of
Read Select
CLKB. The B0-B35 outputs are in the HIGH impedance state when
W/RB is LOW.
PIN DESCRIPTIONS (CONTINUED)
NOTE:
1. BM, SIZE and
SPM are not TTL compatible. These inputs should be tied to GND or VCC.
相關(guān)PDF資料
PDF描述
MS27497T20F16SA CONN RCPT 16POS WALL MNT W/SCKT
LTC2846CG#TR IC TXRX 3.3V MULTIPROTCOL 36SSOP
VI-B4W-MX-B1 CONVERTER MOD DC/DC 5.5V 75W
VE-BNF-MX-B1 CONVERTER MOD DC/DC 72V 75W
LTC2846CG IC TXRX 3.3V MULTIPROTCOL 36SSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT723624L15PFG 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 128TQFP
IDT723624L15PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 128TQFP
IDT723626L12PF 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723626L12PF8 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723626L15PF 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*